Probe wafer, probe device, and testing system

A probe apparatus electrically connected to a semiconductor wafer on which a plurality of semiconductor chips are formed, the probe apparatus comprising:

• a probe wafer for pitch conversion that is electrically connected to the semiconductor wafer;
• and
• a probe wafer for circuit formation that is electrically connected to the probe wafer for pitch conversion, wherein
• the probe wafer for pitch conversion includes:
• a wafer substrate for pitch conversion;
• a plurality of wafer connection terminals formed on a surface of the wafer substrate for pitch conversion that opposes the semiconductor wafer, at least one wafer connection terminal being provided for each one of the semiconductor chips and electrically connected to an input/output terminal of the corresponding semiconductor chip;
• a plurality of first intermediate connection terminals formed on a surface of the wafer substrate for pitch conversion that opposes the probe wafer for circuit formation in one-to-one relation with the plurality of wafer connection terminals at an interval different from an interval of the wafer connection terminals, to be electrically connected to the probe wafer for circuit formation;
• and
• a plurality of transfer paths, each of which electrically connects a corresponding wafer connection terminal to a first intermediate connection terminal, and
• the probe wafer for circuit formation includes:
• a wafer substrate for circuit formation provided to oppose a surface of the wafer substrate for pitch conversion on which the plurality of intermediate connection terminals are provided;
• a plurality of second intermediate connection terminals provided on the wafer substrate for circuit formation in one-to-one relation with the plurality of first intermediate connection terminals, each second intermediate connection terminal electrically connected to a corresponding one of the first intermediate connection terminals;
• and
• a plurality of circuit sections provided so that at least one circuit section is provided for each one of the semiconductor chips, generates a signal to the corresponding semiconductor chip, and supplies a signal to the corresponding semiconductor chip via the intermediate connection terminals and the wafer connection terminal.