Semiconductor device for battery power voltage control

A semiconductor device, comprising:

• a first semiconductor chip which has four corners including a first corner and a plurality of first pads provided over a main surface thereof;
• a second semiconductor chip which has four corners including a second corner and a plurality of second pads provided over a main surface thereof, and which is stacked over the main surface of the first semiconductor chip such that both of the main surfaces are directed in the same direction and also the first corner and the second corner are arranged to be close to each other;
• a sealing body sealing the first semiconductor chip and the second semiconductor chip;
• and
• a plurality of external terminals each of which is coupled to parts of the plurality of first and second pads and a part of which is exposed to an outside of the sealing body,
• wherein the plurality of the first pads of the first semiconductor chip include:
• an external power supply input pad supplied with an external power supply voltage from the external terminal;
• a regulator circuit which is electrically connected with the external power supply input pad and generates an internal power supply voltage by stepping down the external power supply voltage according to a reference voltage and an input voltage to be compared with this reference voltage;
• an internal power supply voltage output pad which is electrically connected to the regulator circuit and from which the internal power supply voltage is output;
• and
• a monitor pad which is electrically connected to an input part of the regulator circuit to which the input voltage is input;
• wherein the plurality of the second pads of the second semiconductor chip include:
• an internal power supply input pad to which the internal power supply voltage is input from the internal power supply voltage output pad;
• wherein the internal power supply voltage output pad and the monitor pad are disposed to be closer to the first corner among the four corners;
• wherein the internal power supply input pad is disposed to be closer to the second corner among the four corners;
• wherein the monitor pad is electrically connected to a coupling path between the internal power supply voltage output pad and the internal power supply input pad or electrically connected to the internal power supply voltage output pad via the internal power supply input pad;
• wherein the first semiconductor chip includes a first signal pad transmitting and receiving a signal to and from the second semiconductor chip along a side different from a side forming the first corner;
• and
• wherein the second semiconductor chip includes a second signal pad electrically connected to the first signal pad along a side close and in parallel to the side along which the first signal pad is disposed.

A semiconductor device, comprising:

• a first semiconductor chip which has a first side, a second side opposite to the first side, a third and a fourth side intersecting the second side, and has a plurality of first pads provided over a main surface thereof;
• a second semiconductor chip which has a fifth side and a sixth side opposite to the fifth side, and has a plurality of second pads provided over a main surface thereof, and which is stacked over the main surface of the first semiconductor chip such that the plurality of pads of the first semiconductor chip are exposed in a first region sandwiched between the first side and the fifth side and in a second region sandwiched between the second side and the sixth side while the third and the fourth sides are covered, and also both of the main surfaces are directed in the same direction;
• a sealing body sealing the first semiconductor chip and the second semiconductor chip;
• and
• a plurality of external terminals each of which is coupled to parts of the plurality of first and second pads and a part of which is exposed to an outside of the sealing body,
• wherein the plurality of the first pads of the first semiconductor chip include:
• an external power supply input pad which is disposed in the first region and supplied with an external power supply voltage from the external terminal;
• a regulator circuit which is disposed in the first region and electrically connected with the external power supply input pad and which generates an internal power supply voltage by stepping down the external power supply voltage according to a reference voltage and an input voltage to be compared with this reference voltage;
• an internal power supply voltage output pad which is disposed in the first region and electrically connected to the regulator circuit and from which the internal power supply voltage is output;
• and
• a monitor pad which is disposed in the first region and electrically connected to an input part of the regulator circuit to which the input voltage is input;
• wherein the plurality of the second pads of the second semiconductor chip include:
• an internal power supply input pad to which the internal power supply voltage is input from the internal power supply voltage output pad;
• wherein the first semiconductor chip includes a first signal pad transmitting and receiving a signal to and from the second semiconductor chip, in the second region;
• and
• wherein the second semiconductor chip includes a second signal pad electrically connected to the first signal pad along the sixth side.

A semiconductor device, comprising:

• a first semiconductor chip which has four sides including a first side and a plurality of first pads provided over a main surface thereof;
• a second semiconductor chip which has four sides including a second side and a plurality of second pads provided over a main surface thereof, and which is stacked over the main surface of the first semiconductor chip such that the first side and the second side are arranged to be close and in parallel to each other and also both of the main surfaces are directed in the same direction;
• a sealing body sealing the first semiconductor chip and the second semiconductor chip;
• and
• a plurality of external terminals each of which is coupled to parts of the plurality of first and second pads and a part of which is exposed to an outside of the sealing body,
• wherein the plurality of the first pads of the first semiconductor chip include:
• an external power supply input pad supplied with an external power supply voltage from the external terminal;
• a regulator circuit which is electrically connected to the external power supply input pad and generates an internal power supply voltage by stepping down the external power supply voltage according to a reference voltage and an input voltage to be compared with this reference voltage;
• an internal power supply voltage output pad which is electrically connected to the regulator circuit and from which the internal power supply voltage is output;
• and
• a monitor pad which is electrically connected to an input part of the regulator circuit to which the input voltage is input;
• wherein the plurality of the second pads of the second semiconductor chip include:
• an internal power supply input pad to which the internal power supply voltage is input from the internal power supply voltage output pad;
• wherein the internal power supply voltage output pad and the monitor pad are disposed along the first side of the first semiconductor chip;
• wherein the internal power supply input pad is disposed along the second side of the second semiconductor chip;
• and
• wherein the monitor pad is electrically connected to a coupling path between the internal power supply voltage output pad and the internal power supply input pad or electrically connected to the internal power supply voltage output pad via the internal power supply input pad.

A semiconductor device, comprising:

• a first semiconductor chip which has four corners including a first corner and a plurality of first pads provided over a main surface thereof;
• a second semiconductor chip which has four corners including a second corner and a plurality of second pads provided over a main surface thereof, and which is stacked over the main surface of the first semiconductor chip such that both of the main surfaces are directed in the same direction and also the first corner and the second corner are arranged to be close to each other;
• a sealing body sealing the first semiconductor chip and the second semiconductor chip;
• and
• a plurality of external terminals each of which is coupled to parts of the plurality of first and second pads and a part of which is exposed to an outside of the sealing body,
• wherein the plurality of the first pads of the first semiconductor chip include:
• an external power supply input pad supplied with an external power supply voltage from the external terminal;
• a regulator circuit which is electrically connected with the external power supply input pad and generates an internal power supply voltage by stepping down the external power supply voltage according to a reference voltage and an input voltage to be compared with this reference voltage;
• an internal power supply voltage output pad which is electrically connected to the regulator circuit and from which the internal power supply voltage is output;
• and
• a monitor pad which is electrically connected to an input part of the regulator circuit to which the input voltage is input;
• wherein the plurality of the second pads of the second semiconductor chip include:
• an internal power supply input pad to which the internal power supply voltage is input from the internal power supply voltage output pad,
• wherein the internal power supply voltage output pad and the monitor pad are disposed to be closer to the first corner among the four corners,
• wherein the internal power supply input pad is disposed to be closer to the second corner among the four corners, and
• wherein the monitor pad is electrically connected to a coupling path between the internal power supply voltage output pad and the internal power supply input pad or electrically connected to the internal power supply voltage output pad via the internal power supply input pad.

A semiconductor device, comprising:

• a first semiconductor chip which has a first side, a second side opposite to the first side, a third and a fourth side intersecting the second side, and has a plurality of first pads provided over a main surface thereof;
• a second semiconductor chip which has a fifth side and a sixth side opposite to the fifth side, and has a plurality of second pads provided over a main surface thereof, and which is stacked over the main surface of the first semiconductor chip such that the plurality of pads of the first semiconductor chip are exposed in a first region sandwiched between the first side and the fifth side and in a second region sandwiched between the second side and the sixth side while the third and the fourth sides are covered, and also both of the main surfaces are directed in the same direction;
• a sealing body sealing the first semiconductor chip and the second semiconductor chip;
• and
• a plurality of external terminals each of which is coupled to parts of the plurality of first and second pads and a part of which is exposed to an outside of the sealing body,
• wherein the plurality of the first pads of the first semiconductor chip include:
• an external power supply input pad which is disposed in the first region and supplied with an external power supply voltage from the external terminal;
• a regulator circuit which is disposed in the first region and electrically connected with the external power supply input pad and which generates an internal power supply voltage by stepping down the external power supply voltage according to a reference voltage and an input voltage to be compared with this reference voltage;
• an internal power supply voltage output pad which is disposed in the first region and electrically connected to the regulator circuit and from which the internal power supply voltage is output;
• and
• a monitor pad which is disposed in the first region and electrically connected to an input part of the regulator circuit to which the input voltage is input;
• wherein the plurality of the second pads of the second semiconductor chip include:
• an internal power supply input pad to which the internal power supply voltage is input from the internal power supply voltage output pad.