Semiconductor device and method for manufacturing the same

A multi-gate metal oxide silicon transistor, comprising:

• a silicon substrate comprising a convex portion between shallow trench isolation regions;
• a dielectric portion over the convex portion;
• a silicon fin over the dielectric portion;
• a shallow trench isolation layer in the shallow trench isolation regions, the upper surface of the shallow trench isolation layer being located between the lower surface and the upper surface of first dielectric layer;
• a laterally grown silicon portion on a side surface of the silicon fin in a source/drain region that is protruded laterally from the silicon fin in the source/drain region;
• a gate electrode provided over the silicon fin via a gate dielectric layer in a gate electrode region;
• first spacers adjacent to the side surfaces of the gate electrode;
• and
• shallow trench isolation layer between the convex portions.

A method of making a multi-gate metal oxide silicon transistor, comprising:

• forming a silicon germanium layer over a silicon substrate, and forming a silicon layer over the silicon germanium layer;
• forming shallow trench isolation regions, thereby forming, between the shallow trench isolation regions, a convex portion of the silicon substrate, a silicon germanium portion over the convex portion, and a silicon fin over the silicon germanium portion;
• forming a shallow trench isolation layer in the shallow trench isolation regions, the upper surface of the shallow trench isolation layer being located below the upper surface of the convex portion;
• forming a first gate electrode over the silicon fin via a first gate dielectric layer;
• forming first spacers adjacent to the side surfaces of the first gate electrode;
• replacing the silicon germanium portion with a dielectric portion;
• forming second spacers adjacent to the side surfaces of the convex portion;
• and
• laterally growing a silicon portion from the silicon fin in a source/drain region.

A method of making a multi-gate metal oxide silicon transistor, comprising:

• forming a semiconductor layer over a silicon substrate, a silicon germanium layer over the bulk semiconductor layer, and a silicon layer over the silicon germanium layer;
• forming shallow trench isolation regions, thereby forming, between the shallow trench isolation regions, a convex portion of the bulk silicon substrate, a silicon germanium portion over the convex portion, and a silicon fin over the silicon germanium portion;
• forming a shallow trench isolation layer in the shallow trench isolation regions, the upper surface of the shallow trench isolation layer being located between the lower surface and the upper surface of the silicon germanium portion;
• forming a first gate electrode over the silicon fin via a first gate dielectric layer;
• forming first spacers adjacent to the side surfaces of the first gate electrode;
• replacing the silicon germanium portion with a dielectric portion;
• and
• laterally growing a silicon portion from the silicon fin in a source/drain region.