High breakdown voltage semiconductor circuit device

A semiconductor device comprising:

• a silicon support substrate;
• a silicon oxide layer stacked on said silicon support substrate;
• a silicon active layer stacked on said silicon oxide layer;
• and
• a high-breakdown-voltage first conductivity type MOS transistor provided in a first region of said silicon active layer defined by use of dielectric material for isolation extending from a primary surface of said silicon active layer to said silicon oxide layer, wherein said first conductivity type MOS transistor forms a first conductivity type channel and shifts a voltage level of a high voltage gate driving circuit, which supplies a control signal to a gate of a top arm MOS transistor, to a high voltage level, and
• a high-breakdown-voltage second conductivity type MOS transistor, provided in a separate, second region of said silicon active layer defined by use of said dielectric material for isolation extending from said primary surface of said silicon active layer to said silicon oxide layer, wherein said second conductivity type MOS transistor forms a second conductivity type channel and shifts a voltage level of said high voltage gate driving circuit, which supplies a control signal to said gate of said top arm MOS transistor, to a high voltage level,
• wherein:
• said first conductivity type MOS transistor includes:
• drain region implemented by said silicon active layer;
• a doped region located in said silicon active layer and having a conductivity type opposite to that of said silicon active layer;
• and
• a first field oxide layer provided between a source electrode and a drain electrode to adjoin at least part of a surface of said silicon active layer,
• wherein said doped region is formed in an electrically floating state at a position where said silicon active layer adjoins said first field oxide layer, and in a doughnut-shaped planar pattern in said drain region, and is overlapped partly with the source electrode,
• said second conductivity type MOS transistor includes:
• a low impurity concentration drain region and a high impurity concentration drain region, which has an impurity concentration higher than said low impurity concentration drain region, located in said silicon active layer and having a conductivity type opposite to that of said silicon active layer;
• a source electrode and a gate electrode surrounded by said low impurity concentration drain region and said high impurity concentration drain region;
• a doped region located in said low impurity concentration drain region and having a conductivity type opposite to that of said low impurity concentration drain region;
• and
• a second field oxide layer which is provided between said source electrode and said drain regions to adjoin at least part of a surface of said low impurity concentration drain region and part of a surface of said high impurity concentration drain region,
• wherein said doped region is formed in the electrically floating state at a position where said low impurity concentration drain region adjoins said second field oxide layer in a doughnut-shaped planar pattern in said low impurity concentration drain region, and is overlapped partly with the source electrode.

A semiconductor device comprising:

• a silicon support substrate;
• a silicon oxide layer stacked on said silicon support substrate;
• a silicon active layer stacked on said silicon oxide layer;
• and
• a high-breakdown-voltage IGBT provided in a region of said silicon active layer defined by use of dielectric material for isolation extending from a primary surface of said silicon active layer to said silicon oxide layer, wherein:
• said IGBT includes:
• a collector region implemented by said silicon active layer;
• a doped region located in said silicon active layer and having a conductivity type opposite to that of said silicon active layer;
• and
• a field oxide layer provided between an emitter electrode and a collector electrode to adjoin at least part of a surface of said silicon active layer, and
• wherein said doped region is formed in an electrically floating state at a position where said silicon active layer adjoins said field oxide layer and in a doughnut-shaped planar pattern in said collector region, and is overlapped partly with the emitter electrode.