Layout structure of power MOS transistor
AssigneePtek Technology Co., Ltd.
InventorsMing Tang, Shih-Ping Chiao
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Abstract
The present invention discloses a layout structure of a transistor unit of a power MOS transistor, wherein the layout structure comprises a drain area, a plurality of body areas, a plurality of source areas and a gate area. The plurality of body areas surround the drain area. The plurality of source areas extend from the perimeters of the plurality of body areas in an anisotropic manner. The gate area is disposed between the drain area and the plurality of source areas. The contacts of the drain area, the plurality of body areas and the plurality of source areas are all disposed on the same side of the layout structure.
Claims16
A power MOS transistor comprising a plurality of transistor units, a layout structure of the transistor unit comprising:
- a drain area;
- a plurality of body areas surrounding the drain area;
- a plurality of source areas extending outward from the perimeter of each of the plurality of body areas in an anisotropic manner;
- a gate area disposed between the drain area and the plurality of source areas;
- and
- at least three conductive lines connecting adjacent gate areas;
- wherein contacts of the drain area, the plurality of body areas and the plurality of source areas are disposed on the same side of the layout structure, and the transistor unit comprises spatial symmetry with respect to the center of the transistor unit.
A power MOS transistor comprising a plurality of transistor units, a layout structure of the transistor unit comprising:
- a drain area;
- a plurality of body areas surrounding the drain area;
- a plurality of source areas extending outward from each side of each of the plurality of body areas;
- a gate area disposed between the drain area and the plurality of source areas;
- and
- at least three conductive lines connecting adjacent gate areas;
- wherein contacts of the drain area, the plurality of body areas and the plurality of source areas are disposed on the same side of the layout structure, and the transistor unit comprises spatial symmetry with respect to the center of the transistor unit.
Dependencies are inferred from the claim text.