Nanowire transistor with surrounding gate
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
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Abstract
One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.
Claims26
A transistor array comprising a plurality of transistors arranged in rows and columns, wherein a lithographic process is used to fabricate features used to form the transistors in the array, and wherein the lithographic process is constrained by a minimum feature size, each transistor in the transistor array comprising:
- a crystalline substrate;
- a first source/drain region formed in the crystalline substrate;
- a crystalline semiconductor pillar formed on the substrate in contact with the first source/drain region, the semiconductor pillar having cross-section dimensions less than the minimum feature size;
- a second source/drain region formed in a top portion of the pillar;
- a gate insulator formed around the pillar;
- and
- a surrounding gate formed around and separated from the pillar by the gate insulator.
A transistor array comprising a plurality of transistors arranged in rows and columns, wherein a lithographic process is used to fabricate features used to form the transistors in the array and wherein the lithographic process is constrained by a minimum feature size, each transistor in the transistor array comprising:
- a crystalline silicon substrate;
- a first source/drain region formed in the crystalline silicon substrate;
- a crystalline silicon pillar formed on the substrate in contact with the first source/drain region, the silicon pillar having cross-section dimensions less than a minimum feature size;
- a second source/drain region formed in a top portion of the pillar;
- a gate insulator formed around the pillar;
- a surrounding gate formed around and separated from the pillar by the gate insulator;
- and
- a gate contact positioned adjacent to and in contact with the surrounding gate, the surrounding gate and the gate contact being etched to have a top surface below a top surface of the pillar.
A transistor array comprising a plurality of transistors arranged in rows and columns, wherein a lithographic process is used to fabricate features used to form the transistors in the array, and wherein the lithographic process is constrained by a minimum feature size, each transistor in the transistor array comprising:
- a crystalline silicon substrate;
- a first source/drain region formed in the crystalline silicon substrate;
- a crystalline silicon pillar formed on the substrate in contact with the first source/drain region, the silicon pillar having cross-section dimensions less than a minimum feature size;
- a second source/drain region formed in a top portion of the pillar;
- a gate insulator formed around the pillar;
- a surrounding gate formed around and separated from the pillar by the gate insulator;
- and
- at least one gate line positioned adjacent to and in contact with the surrounding gate, the surrounding gate and the gate line being etched to have a top surface below a top surface of the pillar.
A semiconductor structure, wherein a lithographic process is used to fabricate features used to form the structure and wherein the lithographic process is constrained by a minimum feature size, the structure comprising:
- a crystalline substrate;
- and
- a semiconductor pillar formed on the substrate in contact with the first source/drain region, the semiconductor pillar having cross-section dimensions less than the minimum feature size, the semiconductor pillar having a crystallized bottom portion and an amorphous top portion indicative of a partially-completed solid phase epitaxy (SPE) process.
Dependencies are inferred from the claim text.