Integrated circuit having gate electrode level region including at least seven linear-shaped conductive structures at equal pitch including linear-shaped conductive structure forming transistors of two different types and at least three linear-shaped conductive structures having aligned ends

A method for creating a layout of an integrated circuit, comprising:

• operating a computer to define a layout of a gate electrode level region to include a number of conductive structure layout shapes,
• wherein each conductive structure layout shape within the layout of the gate electrode level region is linear-shaped and formed to extend lengthwise in a first direction and has a lengthwise centerline that extends in the first direction,
• wherein each conductive structure layout shape within the layout of the gate electrode level region is positioned according to an equal pitch as measured in a second direction perpendicular to the first direction, such that a distance as measured in the second direction between lengthwise centerlines of different ones of the conductive structure layout shapes within the layout of the gate electrode level region is an integer multiple of the equal pitch,
• wherein each conductive structure layout shape within the layout of the gate electrode level region is positioned next to and spaced apart from an adjacent conductive structure layout shape in accordance with the equal pitch,
• wherein the number of conductive structure layout shapes in the layout of the gate electrode level region includes seven conductive structure layout shapes positioned in a side-by-side and spaced apart manner such that a lengthwise centerline-to-lengthwise centerline distance between adjacent ones of the seven conductive structure layout shapes as measured in the second direction is substantially equal to the equal pitch,
• wherein the layout of the gate electrode level region extends outward from an outermost lost periphery of the seven conductive structure layout shapes by a distance of about 965 nanometers, and wherein the layout of the gate electrode level region is a portion of a layout of a gate electrode level of the integrated circuit,
• wherein at least one of the seven conductive structure layout shapes forms both a gate electrode of a transistor of a first transistor type and a gate electrode of a transistor of a second transistor type, and
• wherein each of at least three of the seven conductive structure layout shapes has an end aligned to a common position in the first direction.

A computer readable medium having computer executable program instructions stored thereon for creating a layout of an integrated circuit, comprising:

• program instructions for defining a layout of a gate electrode level region to include a number of conductive structure layout shapes,
• wherein each conductive structure layout shape within the layout of the gate electrode level region is linear-shaped and formed to extend lengthwise in a first direction and has a lengthwise centerline that extends in the first direction,
• wherein each conductive structure layout shape within the layout of the gate electrode level region is positioned according to an equal pitch as measured in a second direction perpendicular to the first direction, such that a distance as measured in the second direction between lengthwise centerlines of different ones of the conductive structure layout shapes within the layout of the gate electrode level region is an integer multiple of the equal pitch,
• wherein each conductive structure layout shape within the layout of the gate electrode level region is positioned next to and spaced apart from an adjacent conductive structure layout shape in accordance with the equal pitch,
• wherein the number of conductive structure layout shapes in the layout of the gate electrode level region includes seven conductive structure layout shapes positioned in a side-by-side and spaced apart manner such that a lengthwise centerline-to-lengthwise centerline distance between adjacent ones of the seven conductive structure layout shapes as measured in the second direction is substantially equal to the equal pitch,
• wherein the layout of the gate electrode level region extends outward from an outermost periphery of the seven conductive structure layout shapes by a distance of about 965 nanometers, and wherein the layout of the gate electrode level region is a portion of a layout of a gate electrode level of the integrated circuit,
• wherein at least one of the seven conductive structure layout shapes forms both a gate electrode of a transistor of a first transistor type and a gate electrode of a transistor of a second transistor type, and
• wherein each of at least three of the seven conductive structure layout shapes has an end aligned to a common position in the first direction.