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US 8,134,157 B2Granted
Semiconductor device and method of manufacturing same
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsEtsuko Fujimoto, Satoshi Murakami, Shunpei Yamazaki, Shingo Eguchi
Life of this patent
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Abstract
A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.
Claims26
A semiconductor device comprising:
- a CMOS circuit, wherein the CMOS circuit contains a n-channel thin film transistor and a p-channel thin film transistor;
- each of the n-channel thin film transistor and the p-channel thin film transistor comprising:
- a semiconductor region;
- and
- a gate electrode over the semiconductor region with a gate insulating layer interposed between the semiconductor region and the gate electrode,
- wherein a bottom surface of the gate electrode of the n-channel thin film transistor has a different width from that of the p-channel thin film transistor,
- wherein a taper angle of the gate electrode of the n-channel thin film transistor is different from that of the p-channel thin film transistor, and
- wherein the gate insulating layer of the n-channel thin film transistor has a tapered portion.
5 more elements
A semiconductor device comprising:
- a CMOS circuit, wherein the CMOS circuit contains a n-channel thin film transistor and a p-channel thin film transistor;
- each of the n-channel thin film transistor and the p-channel thin film transistor comprising:
- a semiconductor region;
- and
- a gate electrode over the semiconductor region with a gate insulating layer interposed between the semiconductor region and the gate electrode,
- wherein a bottom surface of the gate electrode of the n-channel thin film transistor has a larger width from that of the p-channel thin film transistor,
- wherein a taper angle of the gate electrode of the n-channel thin film transistor is different from that of the p-channel thin film transistor,
- wherein the gate insulating layer of the n-channel thin film transistor has a tapered portion.
5 more elements
A semiconductor device comprising:
- a CMOS circuit, wherein the CMOS circuit contains a n-channel thin film transistor and a p-channel thin film transistor;
- each of the n-channel thin film transistor and the p-channel thin film transistor comprising:
- a semiconductor region;
- a gate electrode over the semiconductor region with a gate insulating layer interposed between the semiconductor region and the gate electrode;
- and
- an interlayer insulating film over the gate electrode,
- wherein a bottom surface of the gate electrode of the n-channel thin film transistor has a different width from that of the p-channel thin film transistor,
- wherein a taper angle of the gate electrode of the n-channel thin film transistor is different from that of the p-channel thin film transistor, and
- wherein the gate insulating layer of the n-channel thin film transistor has a tapered portion.
6 more elements
A semiconductor device comprising:
- a CMOS circuit, wherein the CMOS circuit contains a n-channel thin film transistor and a p-channel thin film transistor;
- each of the n-channel thin film transistor and the p-channel thin film transistor comprising:
- a semiconductor region;
- a gate electrode over the semiconductor region with a gate insulating layer interposed between the semiconductor region and the gate electrode;
- and
- an interlayer insulating film over the gate electrode,
- wherein a bottom surface of the gate electrode of the n-channel thin film transistor has a larger width from that of the p-channel thin film transistor,
- wherein a taper angle of the gate electrode of the n-channel thin film transistor is different from that of the p-channel thin film transistor, and
- wherein the gate insulating layer of the n-channel thin film transistor has a tapered portion.
6 more elements
Dependencies are inferred from the claim text.