Tunneling transistor with barrier
AssigneeNXP B.V.
InventorsGodefridus Hurkx, Prabhat Agarwal
Life of this patent
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Abstract
The invention suggests a transistor (21) comprising a source (24) and a drain (29) as well as a barrier region (27) located between the source and the drain. The barrier region is separated from the source and the drain by intrinsic or lowly doped regions (26, 28) of a semiconductor material. Potential barriers are formed at the interfaces of the barrier region and the intrinsic or lowly doped regions. A gate electrode (32) is provided in the vicinity of the potential barriers such that the effective height and/or width of the potential barriers can be modulated by applying an appropriate voltage to the gate electrode.
Claims14
Transistor comprising a source and a drain as well as a barrier region located between the source and the drain, wherein the barrier region is separated from the source and the drain by intrinsic or lowly doped regions of a semiconductor material, and potential barriers are formed at the interfaces of the barrier region and the intrinsic or lowly doped regions, wherein a gate electrode is provided in the vicinity of the potential barriers such that the effective height and/or width of the potential barriers can be modulated by applying an appropriate voltage to the gate electrode, wherein the barrier region is a highly doped semiconductor material, wherein the transistor is realized as a nanowire, and wherein the nanowire comprises a longitudinal heterostructure.
Dependencies are inferred from the claim text.