Memory device constructions, memory cell forming methods, and semiconductor construction forming methods

A memory cell forming method comprising:

• providing a substrate;
• forming, over the substrate, a horizontally extending memory material disposed to be selectively and reversibly configured in one of two or more different resistive states;
• forming a row line over the memory material;
• forming a vertically extending insulative material laterally adjacent to the memory material and the row line;
• forming a first portion of a diode laterally adjacent to the insulative material, the first portion extending vertically to a position elevationally higher than the memory material and the row line;
• forming a second portion of the diode extending horizontally above the first portion of the diode, the second portion being in direct physical contact with the first portion;
• forming a horizontally extending column line over the second portion of the diode;
• and
• wherein the memory cell is configured to conduct a current between the column line and the row line via the diode and the memory material.

A memory cell forming method comprising:

• providing a substrate;
• forming a first portion of a diode above the substrate;
• forming a second portion of the diode above the first portion of the diode;
• forming a horizontally extending column line over the second portion of the diode;
• forming a vertically extending insulative material laterally adjacent to the column line and the second portion of the diode;
• forming a vertically extending memory material laterally adjacent to the insulative material and in contact with the first portion of the diode, the memory material being disposed to be selectively and reversibly configured in one of two or more different resistive states;
• forming a vertically extending conductive material laterally adjacent to the memory material and in contact with the memory material;
• forming a horizontally extending row line over the column line and the vertically extending conductive material and in contact with the vertically extending conductive material;
• and
• wherein the memory cell is configured to conduct a current between the column line and the row line via the diode and the memory material.

A memory cell, comprising:

• first and second electrodes;
• memory material and a diode in series between and with the first and second electrodes;
• and
• electrically conductive material in series between and with the memory material and the diode;
• wherein the diode is configured to conduct a first current from the second electrode to the first electrode via the memory material and the electrically conductive material, and
• further comprising:
• a third electrode, the memory cell being configured to conduct a second current from the third electrode to the second electrode via the electrically conductive material and the memory material.

A memory cell, comprising:

• first and second electrodes;
• memory material and a diode in series between and with the first and second electrodes;
• and
• electrically conductive material in series between and with the memory material and the diode;
• wherein the diode is configured to conduct a first current from the first electrode to the second electrode via the electrically conductive material and the memory material, and
• further comprising:
• a third electrode, the memory cell being configured to conduct a second current from the second electrode to the third electrode via the memory material and the electrically conductive material.