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US 8,133,818 B2Granted
Method of forming a hard mask pattern in a semiconductor device
AssigneeHynix Semiconductor Inc.
InventorWoo Yung Jung
Life of this patent
Estimating the term…
Abstract
In a method of forming a hard mask pattern in a semiconductor device, only processes for forming patterns having a row directional line shape and a column directional line shape on a plane are performed so that the hard mask patterns can be formed to define densely disposed active regions. A pitch of the hard mask patterns is less than a resolution limit of an exposure apparatus.
Claims21
A method of forming a hard mask pattern in a semiconductor device, the method comprising:
- forming first etching mask patterns over a hard mask layer formed on a semiconductor substrate;
- forming second etching mask patterns including first patterns and second patterns over the semiconductor substrate, the first patterns intersecting the first etching mask patterns, each second pattern being disposed between the first etching mask patterns;
- forming third etching mask patterns over the semiconductor substrate after forming the second etching mask patterns including the first patterns and the second patterns, each third etching mask pattern being disposed between the first patterns and intersecting the first etching mask patterns;
- performing a first etching process such that the first etching mask patterns remain on regions at which the first patterns intersect the first etching mask patterns and the second patterns remain on regions at which the first patterns intersect the second patterns;
- and
- patterning the hard mask layer through a second etching process utilizing the remaining first etching mask patterns and the second patterns as an etching mask to form hard mask patterns.
3 more elements
A method of forming a hard mask pattern in a semiconductor device, the method comprising;
- forming a first etching mask patterns over a hard mask layer provided on a semiconductor substrate;
- forming second etching mask patterns over the semiconductor substrate such that each second etching mask pattern is disposed between the first etching mask patterns, wherein each second etching mask pattern comprises a first pattern and a second pattern, the first patterns intersecting the first etching mask patterns;
- forming third etching mask patterns over the semiconductor substrate after forming the second etching mask patterns including the first patterns and the second patterns, wherein each third etching mask pattern is disposed between the first patterns and intersects the first etching mask patterns;
- performing first etching the first etching mask patterns and the second patterns such that the first etching mask patterns remain on regions at which the first patterns intersect the first etching mask patterns and the second patterns remain on regions at which the first patterns intersect the second patterns;
- and
- performing second etching utilizing the first etching mask patterns and the second patterns as an etching mask to form hard mask patterns, wherein the hard mask patterns correspond to active regions of the semiconductor substrate, the active regions being arranged in a matrix shape.
3 more elements
Dependencies are inferred from the claim text.