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US 8,133,801 B1Granted
Method for forming a semiconducting layer with improved gap filling properties
AssigneeSpansion LLC
InventorsRinji Sugino, Yider Wu, Minh Van Ngo, Jeffrey Sinclair Glick, Kuo-Tung Chang
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Abstract
A method of manufacturing a memory device includes forming a first dielectric layer over a substrate, forming a charge storage element over the first dielectric layer and forming an inter-gate dielectric over the charge storage element. The method also includes depositing a silicon control gate layer over the inter-gate dielectric using a reactant that contains chlorine.
Claims15
A method of manufacturing a memory device, the method comprising:
- forming a first dielectric layer over a substrate;
- forming a charge storage element over the first dielectric layer in one layer;
- forming an inter-gate dielectric over and directly contacting the first dielectric layer and the charge storage element, where the inter-gate dielectric includes a plurality of layers;
- depositing a polysilicon layer directly over the inter-gate dielectric, where depositing the polysilicon control gate layer includes:
- providing a SiH2Cl2 reactant to a deposition chamber at a first flow rate, and
- providing a SiH4 reactant to the deposition chamber at a second flow rate,
- where the SiH2Cl2 and SiH4 reactants are concurrently provided to the deposition chamber,
- planarizing the polysilicon layer to form a control gate;
- forming an interlayer dielectric on the control gate;
- and
- forming a contact hole in the interlayer dielectric.
8 more elements
A method of forming a semiconductor device, the method comprising:
- forming a first dielectric layer over a substrate;
- forming a plurality of charge storage structures over the first dielectric layer, where each of the plurality of charge storage structures is formed in one layer;
- forming an inter-gate dielectric over and directly contacting along a longitudinal length of the first dielectric layer and the plurality of charge storage structures, where the inter-gate dielectric includes an oxide-nitride-oxide stack, and where an opening is formed between adjacent ones of the charge storage structures;
- and
- depositing a polysilicon layer directly over the inter-gate dielectric using a chemical vapor deposition process, the polysilicon layer filling the opening, where the step of depositing comprises:
- providing a SiH2Cl2 reactant to a deposition chamber at a first flow rate under a pressure greater than 1 Torr, and
- providing a SiH4 reactant to the deposition chamber at a second flow rate under a pressure greater than 1 Torr,
- where a ratio of the first flow rate to the second flow rate ranges from approximately 1:10 to approximately 10:1,
- planarizing the polysilicon layer to form a control gate;
- forming an interlayer dielectric on the control gate;
- and
- forming a contact hole in the interlayer dielectric.
9 more elements
A method of forming a semiconductor device, the method comprising:
- forming a first dielectric layer over a substrate;
- forming a plurality of charge storage structures over the first dielectric layer, where each of the plurality of charge storage structures is formed in one layer;
- forming an inter-gate dielectric over and directly contacting along a longitudinal length of the first dielectric layer and the plurality of charge storage structures, where the inter-gate dielectric includes a layer of silicon nitride between first and second layers of silicon oxide, and where an opening is formed between adjacent ones of the charge storage structures;
- and
- depositing a polysilicon layer over the inter-gate dielectric, the polysilicon layer filling the opening, where the depositing comprises:
- depositing, under a pressure greater than 1 Torr, at least a portion of the polysilicon layer by concurrently providing SiH2Cl2 and SiH4 reactants to a deposition chamber at first and second flow rates, respectively,
- where a ratio of the first flow rate to the second flow rate ranges from approximately 1:10 to approximately 10:1,
- planarizing the polysilicon layer to form a control gate;
- forming an interlayer dielectric on the control gate;
- and
- forming a contact hole in the interlayer dielectric.
8 more elements
Dependencies are inferred from the claim text.