Method for reducing capacitance variation between capacitors
AssigneeUnited Microelectronics Corp.
InventorsVictor-Chiang Liang, Chien-Kuo Yang, Hua-Chou Tseng, Chun-Yao Ko, Cheng-Wen Fan, Yu-Ho Chiang, Chih-Yuh Tzeng
Life of this patent
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Abstract
A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.
Claims26
A method for reducing capacitance variations of capacitors, comprising:
- forming at least a first capacitor set and a second capacitor set on a substrate, comprising:
- forming a plurality of first capacitor units connected in parallel to constitute the first capacitor set and forming a plurality of second capacitor units connected in parrallel to constitute the second capacitor set,
- wherein the first capacitor units and the second capacitor units are the same in number, have identical capacitance per capacitor unit, and are spatially intermixed with each other to form a multidimensional array.
A method for reducing capacitance variations of capacitors, comprising:
- forming a plurality of first capacitor units in communication with each other on a substrate, the plurality of first capacitor units being spatially isolated from each other;
- and
- forming a plurality of second capacitor units in communication with each other on the substrate, the plurality of second capacitor units being spatially isolated from each other and electrically isolated from the plurality of first capacitor units;
- wherein the first capacitor units and the second capacitor units are the same in number, have identical capacitance per capacitor unit, and are spatially intermixed with each other to form a multidimensional array.
A method for reducing capacitance variations of capacitors, comprising:
- forming at least a first capacitor set and a second capacitor set on a substrate, comprising:
- forming a plurality of first capacitor units connected in parallel to constitute the first capacitor set and forming a plurality of second capacitor units connected in parallel to constitute the second capacitor set,
- wherein the first capacitor units and the second capacitor units are the same in number, have identical capacitance per capacitor unit, and are spatially intermixed with each other to form a multidimensional array, the first and the second capacitor units are arranged in a three-dimensional (3D) array and are arranged alternately in each of three dimensional directions of the 3D array.
A method for reducing capacitance variations of capacitors, comprising:
- forming a plurality of first capacitor units in communication with each other on a substrate, the plurality of first capacitor units being spatially isolated from each other;
- and
- forming a plurality of second capacitor units in communication with each other on the substrate, the plurality of second capacitor units being spatially isolated from each other and electrically isolated from the plurality of first capacitor units;
- wherein the first capacitor units and the second capacitor units are the same in number, have identical capacitance per capacitor unit, and are spatially intermixed with each other to form a multidimensional array, the first and the second capacitor units are arranged in a three-dimensional (3D) array and are arranged alternately in each of three dimensional directions of the 3D array.
Dependencies are inferred from the claim text.