Transistors with laterally extended active regions and methods of fabricating same
AssigneeSamsung Electronics Co., Ltd.
InventorsSung-Sam Lee, Min-Hee Cho
Life of this patent
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Abstract
A transistor and method of fabricating the transistor are disclosed. The transistor is disposed in an active region of a substrate defined by an isolation region and includes a gate electrode and associated source/drain regions. The isolation region includes an upper isolation region and an lower isolation region, wherein the upper isolation region is formed with sidewalls having, at least in part, a positive profile.
Claims20
A method of fabricating a transistor, the method comprising:
- forming an isolation trench in a substrate to define an active region, the isolation trench comprising an upper isolation trench having sidewalls including, at least in part, a negative profile and a lower isolation trench formed through a bottom surface of the upper isolation trench, wherein the lower isolation trench has a width less than or equal to a minimal width of the upper isolation trench, and wherein the upper isolation trench defines an upper active region in the active region and the lower isolation trench defines a lower active region in the active region having a width greater than or equal to the width of the upper active region;
- filling the isolation trench with an insulating material;
- forming a gate electrode extending through the upper active region into the lower active region;
- and
- forming source/drain regions in the active region on respective sides of the gate electrode.
A method of forming a recessed channel array transistor (RCAT) in an active region of a semiconductor substrate, the method comprising:
- forming a recessed channel region in the substrate to separate source/drain regions of the RCAT and define a channel between the source/drain regions;
- forming a gate electrode structure in the recessed channel region contacting the source/drain regions;
- separating the active region from an adjacent active region by forming an isolation trench in the substrate and filling the isolation trench with an insulating material,
- wherein formation of the isolation trench reduces the contact area between the gate electrode structure and the source/drain regions, and reduces the size of a depletion region associated with the channel without reducing the width of the channel.
A method of fabricating a transistor, the method comprising:
- forming an upper isolation trench in a substrate to define an upper active region;
- forming a lower isolation trench in the substrate to define a lower active region, the lower isolation trench passing through a bottom surface of the upper isolation trench, wherein a width of a lower portion of the lower isolation trench is greater than a width of an upper portion of the lower isolation trench;
- filing the upper and the lower isolation trenches with an insulating material;
- forming a gate electrode extending through the upper active region;
- and
- forming source/drain regions in the upper active region on respective sides of the gate electrode.
Dependencies are inferred from the claim text.