SOI radio frequency switch with enhanced electrical isolation

A method of operating a semiconductor device comprising:

• providing a semiconductor device including:
• at least two field effect transistors located on a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate;
• a shallow trench isolation structure laterally abutting said at least two field effect transistors;
• and
• at least one conductive via extending from a top surface of a middle-of-line (MOL) dielectric layer through said MOL dielectric layer, said shallow trench isolation structure, a buried insulator layer, and to a top surface of a bottom semiconductor layer of said SOI substrate, wherein said at least one conductive via is interposed between said at least two field effect transistors and separates said at least two field effect transistors, and said at least one conductive via laterally surrounds said at least two field effect transistors and does not contact any semiconductor material in said top semiconductor layer;
• applying a radio frequency (RF) signal to at least one of said at least two field effect transistors, wherein an induced charge layer is formed directly underneath said buried insulator layer;
• and
• electrically biasing said bottom semiconductor layer of said SOI substrate and said at least one conductive via at a constant voltage.

A method of forming a semiconductor structure comprising:

• forming a shallow trench isolation structure laterally surrounding at least one portion of a top semiconductor layer and contacting a top surface of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate;
• forming a field effect transistor on each of said at least one portion;
• forming a middle-of-line (MOL) dielectric layer over said at least one field effect transistor and said shallow trench isolation structure;
• and
• forming at least one conductive via extending from a top surface of said MOL dielectric layer through said MOL dielectric layer, said shallow trench isolation structure, a buried insulator layer, and to a top surface of a bottom semiconductor layer of said SOI substrate, wherein said at least one conductive via is laterally spaced from any semiconductor material in said top semiconductor layer by said shallow trench isolation structure and said at least one conductive via laterally surrounds said at least one portion of said top semiconductor layer.