ONO spacer etch process to reduce dark current

#This application claims priority to Chinese Application No. 200810040366.6, filed Jul. 8, 2008, commonly assigned, and hereby incorporated by reference for all purposes.

#The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method and a structure for manufacturing a CMOS image sensor device having a reduced dark current characteristics for advanced application. But it would be recognized that the invention has a much broader range of applicability.

#Integrated circuits have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Conventional integrated circuits provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of integrated circuits.

#FIG. 1 is a simplified diagram illustrating a conventional method of fabricating a CMOS image sensor

#FIG. 2 is a simplified process flow diagram exemplified a method for forming a CMOS image device according to an embodiment of the present invention

#FIG. 3-9 are simplified diagrams illustrating a method of forming a CMOS image sensor according to an embodiment of the present invention.

#According to the present invention, techniques directed to integrated circuits and their processing for the manufacture of semiconductor devices are provided. In particular, the invention provides a method for manufacturing CMOS image sensor integrated circuit device. More particularly, the invention provides a method for manufacturing CMOS image sensor having a reduced dark current. But it would be recognized that the embodiments according to the present invention have a much broader range of applicability. Details of the present invention can be found throughout the present specification and more particularly below.

#CMOS image sensors are emerging as a preferred technology for digital consumer applications. To enable improved pixel sensing performance, CMOS image sensor technology requires improved pixel layout design and integrated circuit processing. Dark current is a major factor influencing sensor performance especially under a low light condition. Factors that may contribute to dark current include defects on the silicon surface and silicon-gate oxide interface in photodiode regions and surrounding regions. Convention fabrication techniques may become in-effective for high density pixel CMOS image sensor layout. FIG. 1 is a simplified diagram illustrating a conventional method of fabricating a CMOS image sensor. As shown, a semiconductor substrate 101 is provided. For example, the semiconductor substrate can be single crystal silicon doped using a P-type impurity. Also shown in FIG. 1 is a photodiode region 103 doped with N type impurities. A P type impurity region 105 is formed overlying the photodiode region or a pinned photodiode structure is shown. The P-type impurities on the surface is provided to prevent surface dark current leakage. The conventional method of fabricating the CMOS image sensor also includes forming a gate structure 107 overlying a gate oxide layer 111. The gate oxide layer can be a grown thermal oxide. The conventional method includes steps of implantation in source/drain regions and channel regions. Thereafter, a blanket dielectric layer is deposited overlying the gate structure. The blanket dielectric layer often includes silicon oxide. The blanket dielectric layer is subjected to an anisotropic etch process to form spacer structures overlying portions of the gate structure. In the conventional method, the spacer etch step also includes masking the photodiode region to prevent damage to the thermal oxide overlying the photodiode region. For example, the photodiode region can be masked using photoresist material to mask the blanket dielectric layer overlying the photodiode region. The blanket dielectric layer remains on the photodiode region. In this instant, the blanket dielectric layer is limited to materials that are transmissible to light, such as silicon dioxide. However, certain dielectric material may impede light transmission to the photo sensitive regions and hence performance of the CMOS image sensor device. These and other limitations would be described in more detailed in the present specification and particularly below.

#FIG. 2 is a simplified process flow diagram exemplified a method 200 for forming a CMOS image device according to an embodiment of the present invention. As shown, the method includes providing a semiconductor substrate (Step 201). The semiconductor substrate can be a single crystal silicon, silicon on insulator, silicon germanium, or the like. In a specific embodiment, the semiconductor substrate is a silicon substrate doped with a suitable impurity. In a preferred embodiment, the silicon substrate is doped with a P type impurity such as boron. The method includes forming a gate dielectric layer (Step 203) overlying the semiconductor substrate. The gate dielectric layer can be formed using a grown oxide such as thermal oxide. Other dielectric material may also be used. The method includes forming gate structures overlying portions of the gate dielectric layer (Step 205). The method includes providing a photosensitive region within a portion of the semiconductor substrate (Step 207). The photosensitive region can be formed using an implant process. For a P-type silicon substrate, the photosensitive region can be doped using a N type impurity. Example of such N-type impurity may include arsenic, antimony, phosphorus, and the like. The method also forms a blanket dielectric layer overlying the semiconductor substrate and the gate structure (Step 209). In a specific embodiment, the blanket dielectric layer comprises a composite dielectric such as an ONO layer. The ONO layer includes a bottom silicon oxide layer, a middle silicon nitride layer, and a top silicon oxide layer. Of course there can be other variations, modifications, and alternatives.