Apparatus and method for processing wirelessly communicated data and clock information within an electronic device

An electronic device (12) for processing information that includes data and clock information and that is wirelessly received from another electronic device (14), the electronic device (12) comprising:

• a first processor (18) that controls operations associated only with wireless communications with the another electronic device (14) and excluding operations associated only with the electronic device (12), the information wirelessly received by the electronic device from the another electronic device comprising at least one information packet containing the data and clock information, a preamble that precedes the at least one information packet and a start command that follows the preamble and that precedes the at least one information packet, the first processor (18) configured to extract the preamble, the start command and the at least one information packet from the information wirelessly received by the electronic device (12) from the another electronic device (14),
• a second processor (16) that controls the operations associated only with the electronic device (12) and excluding the operations associated with the wireless communications with the another device (14),
• a phase lock loop circuit (56) having an input connected to the first processor (18) a first output connected to the second processor (16) and a second output, the phase lock loop circuit (56) being normally in a sleep state and configured to be responsive to the preamble to wake up from the sleep state and to lock and run with a phase lock loop clock that operates at a phase lock loop clock rate, wherein the phase lock loop circuit (56) extracts the clock information from the at least one information packet and produces the clock signal and
• a decoder circuit (58) having a first input connected to the first processor (18), a second input connected to the phase lock loop circuit (56) and an output connected to the second processor (16), wherein the decoder circuit (58) decodes the data from the at least one information packet and produces the data, the decoder circuit (58) decodes the start command by removing the clock information from the extracted start command as a function of the phase lock loop clock,
• and wherein the decoded start command received by the second processor (16) alerts the second processor (16) that data will subsequently be sent thereto by the another electronic device (14)
• wherein the second processor (16) synchronously receives the data using the clock signal,
• and wherein only the second processor (16) acts upon the data.