Method of maintaining the state of semiconductor memory having electrically floating body transistor
AssigneeZeno Semiconductor, Inc.
InventorsYuniarto Widjaja, Zvi Or-Bach
Life of this patent
Estimating the term…
Abstract
Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.
Claims18
A method of maintaining a state of a memory cell without interrupting access to said memory cell, said method comprising:
- applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell;
- and
- accessing the cell.
A method of operating a memory array having rows and columns of memory cells assembled into an array of said memory cells, each said memory cell having a floating body region for storing data;
- the method comprising:
- performing a holding operation on at least all of said cells not aligned in a row or column of a selected cell;
- and
- accessing said selected cell and performing a read or write operation on said selected cell while performing said hold operation on said at least all of said cells not aligned in a row or column of said selected cell.
A method of operating a memory array having rows and columns of memory cells assembled into an array of said memory cells, each said memory cell having a floating body region for storing data;
- the method comprising:
- refreshing a state of at least one of said memory cells;
- and
- accessing at least one other of said memory cells, wherein access of said at least one other of said memory cells in not interrupted by said refreshing, and wherein said refreshing is performed without alternating read and write operations.
Dependencies are inferred from the claim text.