Integrated circuit with gate electrode level including at least six linear-shaped conductive structures forming gate electrodes of transisters with at least one pair of linear-shaped conductive structures having offset ends

A method for creating a layout of an integrated circuit, comprising:

• operating a computer to define at least six linear conductive structure shapes in a gate electrode level region layout, the at least six linear conductive structure shapes each formed to extend lengthwise in a first direction, the at least six linear conductive structure shapes including—
• a first linear conductive structure shape including a first gate portion that forms a gate electrode of a first transistor of a first transistor type and a second gate portion that forms a gate electrode of a first transistor of a second transistor type, the first linear conductive structure shape also including a non-gate portion that extends in the first direction between the first and second gate portions of the first linear conductive structure shape,
• a second linear conductive structure shape including a gate portion that forms a gate electrode of a second transistor of the first transistor type, the second linear conductive structure shape also including a non-gate portion that extends in the first direction away from the gate portion of the second linear conductive structure shape,
• a third linear conductive structure shape including a gate portion that forms a gate electrode of a second transistor of the second transistor type, the third linear conductive structure shape also including a non-gate portion that extends in the first direction away from the gate portion of the third linear conductive structure shape,
• a fourth linear conductive structure shape including a gate portion that forms a gate electrode of a third transistor of the first transistor type, the fourth linear conductive structure shape also including a non-gate portion that extends in the first direction away from the gate portion of the fourth linear conductive structure shape,
• a fifth linear conductive structure shape including a gate portion that forms a gate electrode of a third transistor of the second transistor type, the fifth linear conductive structure shape also including a non-gate portion that extends in the first direction away from the gate portion of the fifth linear conductive structure shape,
• a sixth linear conductive structure shape including a first gate portion that forms a gate electrode of a fourth transistor of the first transistor type and a second gate portion that forms a gate electrode of a fourth transistor of the second transistor type, the sixth linear conductive structure shape also including a non-gate portion that extends in the first direction between the first and second gate portions of the sixth linear conductive structure shape,
• wherein the second linear conductive structure shape is substantially co-aligned with the third linear conductive structure shape along a common line of extent in the first direction, and wherein the second linear conductive structure shape is separated from the third linear conductive structure shape by a first line end spacing distance,
• wherein the fourth linear conductive structure shape is substantially co-aligned with the fifth linear conductive structure shape along another common line of extent in the first direction, and wherein the fourth linear conductive structure shape is separated from the fifth linear conductive structure shape by a second line end spacing distance,
• wherein the first, second, third, fourth, fifth, and sixth linear conductive structure shapes are defined such that the first, second, third, and fourth transistors of the first transistor type are separated from the first, second, third, and fourth transistors of the second transistor type by a non-active portion of a substrate region over which the gate electrode level region layout is to be fabricated,
• wherein a first end of the second linear-shaped conductive structure is positioned over the non-active portion of the substrate region,
• wherein a first end of the third linear-shaped conductive structure is positioned over the non-active portion of the substrate region,
• wherein a first end of the fourth linear-shaped conductive structure is positioned over the non-active portion of the substrate region,
• wherein a first end of the fifth linear-shaped conductive structure is positioned over the non-active portion of the substrate region, and
• wherein either the first ends of the second and fourth linear-shaped conductive structures are, offset from each other in the first direction, or the first ends of the third and fifth linear-shaped conductive structures are offset from each other in the first direction, or the first ends of the second and fourth linear-shaped conductive structures are offset from each other in the first direction and the first ends of the third and fifth linear-shaped conductive structures are offset from each other in the first direction.