Method for dicing a semiconductor wafer, a chip diced from a semiconductor wafer, and an array of chips diced from a semiconductor wafer

A method for dicing a semiconductor wafer, comprising:

• cutting a reference slot in a back main surface of the wafer;
• cutting a back slot in the back main surface of the wafer, the back slot positioned with respect to the reference slot;
• determining a desired location for a first chip edge with respect to the reference slot;
• applying, using a radiant energy source, radiant energy in a first path such that a first series of reformed regions are formed within the wafer along the first path, wherein:
• a crystalline structure of the wafer is modified in the first series of reformed regions;
• and,
• an alignment of a first edge of the radiant energy source is:
• with respect to the desired location for the first chip edge;
• and,
• in alignment with the back slot;
• determining a desired location for a second chip edge with respect to the reference slot;
• applying radiant energy in a second path such that a second series of reformed regions are formed within the wafer along the second path, wherein:
• the crystalline structure of the wafer is modified in the second series of reformed regions;
• and,
• an alignment of a second edge of the laser is:
• with respect to the desired location for the second chip edge;
• and,
• in alignment with the back slot;
• and,
• separating the wafer along the first and second series of reformed regions to divide portions of the wafer on either side of the first and second series of reformed regions.

A method for dicing a semiconductor wafer, comprising:

• cutting a reference slot in a back main surface of the wafer;
• cutting a back slot in the back main surface of the wafer, the back slot positioned with respect to the reference slot;
• determining a desired location for a chip edge with respect to the reference slot;
• applying, using a radiant energy source, radiant energy in a path such that a series of reformed regions are formed within the wafer along the path, wherein:
• a crystalline structure of the wafer is modified in the reformed regions;
• and,
• an alignment of an edge of the radiant energy source is with respect to the desired location for the chip edge;
• and,
• separating the wafer along the series of reformed regions to divide portions of the wafer on either side of the series of reformed regions, wherein applying radiant energy in the first path such that the first series of reformed regions are formed within the wafer includes forming the first series of reformed regions at an acute angle with respect to the front main surface of the wafer.