3D integrated circuit device fabrication with precisely controllable substrate removal

A method for fabricating a 3D integrated circuit, the method comprising the steps of:

• providing an interface wafer, the interface wafer including a first wiring layer and through-silicon vias;
• providing a first active circuitry layer wafer comprising a P+ portion covered by a P− layer, the P− layer of the first active circuitry layer wafer including active circuitry and through-silicon vias;
• fabricating a second wiring layer at a top surface of the first active circuitry layer wafer;
• performing a high-precision face-to-face alignment of the first active circuitry layer wafer face down to the interface wafer;
• bonding the second wiring layer of the first active circuitry layer wafer directly to the first wiring layer of the interface wafer;
• after bonding the first active circuitry layer wafer to the interface wafer, selectively removing the P+ portion of the first active circuitry layer wafer with respect to the P− layer of the first active circuitry layer wafer;
• after selectively removing the P+ portion of the first active circuitry layer wafer, fabricating a third wiring layer on the backside of the P− layer;
• providing a second active circuitry layer wafer comprising a P+ portion covered by a P− layer, the P− layer of the second active circuitry layer wafer including active circuitry;
• fabricating a fourth wiring layer at a top surface of the second active circuitry layer Wafer;
• performing a high-precision face-to-face alignment of the second active circuitry layer wafer face down to the P− layer of the first active circuitry layer wafer;
• bonding the fourth wiring layer of the second active circuitry layer wafer directly to the third wiring layer on the backside of the P− layer;
• after bonding the second active circuitry layer wafer to the third wiring layer, selectively removing the P+ portion of the second active circuitry layer wafer with respect to the P− layer of the second active circuitry layer wafer;
• after selectively removing the P+ portion of the second active circuitry layer wafer, fabricating a fifth wiring layer on the backside of the P− layer of the second active circuitry layer wafer;
• providing a base wafer, the base wafer including a sixth wiring layer;
• performing a high-precision face-to-face alignment of the P− layer of the second active circuitry layer wafer face down to the base wafer;
• bonding the fifth wiring layer on the backside of the P− layer of the second active circuitry layer wafer directly to the sixth wiring layer of the base wafer;
• and
• after bonding the fifth wiring layer to the base wafer, thinning the interface wafer so as to form an interface layer, and forming metallizations comprising solder bumps on the interface layer, the solder bumps being coupled through the through-silicon vias in the interface layer to the first wiring layer,
• wherein the interface wafer is formed of a material that is not soluble in an etchant used in the selectively removing step to selectively etch the P+ portion of the first active circuitry layer wafer with respect to the P− layer of the first active circuitry layer wafer.