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US 8,127,979 B1Granted
Electrolytic depositon and via filling in coreless substrate processing
AssigneeIntel Corporation
InventorsTao Wu, Nicolas R. Watts
Life of this patent
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Abstract
Electronic assemblies including coreless substrates and their manufacture using electrolytic plating, are described. One method includes providing a core comprising a metal, and forming a dielectric material on the core. The method also includes forming vias in the dielectric material, the vias positioned to expose metal regions. The method also performing an electrolytic plating of metal into the vias and on the metal regions, wherein the core is electrically coupled to a power supply during the electrolytic plating of metal into the vias and delivers current to the metal regions. The method also includes removing the metal core after the electrolytic plating of metal into the vias. Other embodiments are described and claimed.
Claims20
A method comprising:
- providing a core comprising a metal;
- forming a dielectric material on the core;
- forming vias in the dielectric material, the vias positioned to expose metal regions;
- performing an electrolytic plating of metal into the vias and on the metal regions, wherein the core is electrically coupled to a power supply during the electrolytic plating of metal into the vias and delivers current to the metal regions;
- removing the metal core after the electrolytic plating of metal into the vias;
- and
- prior to the forming a dielectric material on the core;
- forming a patterned photoresist layer on the metal core;
- performing an electrolytic plating of at least one metal layer in an opening in the patterned photoresist layer, wherein the core is electrically coupled to a power supply during the electrolytic plating of the at least one metal layer in the opening and delivers current to the at least one metal layer in the opening;
- and
- removing the patterned photoresist layer;
- wherein the forming a dielectric material on the core includes positioning the dielectric material on the core and on the at least one metal layer.
9 more elements
A method comprising:
- providing a core comprising a metal;
- forming a dielectric material on the core;
- forming vias in the dielectric material, the vias positioned to expose metal regions;
- performing an electrolytic plating of metal into the vias and on the metal regions, wherein the core is electrically coupled to a power supply during the electrolytic plating of metal into the vias and delivers current to the metal regions;
- removing the metal core after the electrolytic plating of metal into the vias;
- performing an electroless plating of a layer of metal on the dielectric layer and on the metal in the vias;
- forming a patterned resist layer on the electroless plated layer of metal to define regions for electrically conductive traces;
- and
- performing an electrolytic plating of metal on the regions for electrically conductive traces, to form electrically conductive traces.
6 more elements
A method comprising:
- providing a core comprising a metal;
- forming a dielectric material on the core;
- forming vias in the dielectric material, the vias positioned to expose metal regions;
- performing an electrolytic plating of a metal on the metal regions in the vias;
- wherein the core is coupled to a power supply and delivers current during the electrolytic plating of the metal on the metal regions in the vias;
- wherein the core is used as a plating buss during the electrolytic plating of the metal on the metal regions in the via;
- forming electrically conductive traces on the dielectric material and the electrolytically plated metal in the vias after the electrolytic deposition of the metal into the vias;
- forming a solder resist layer on the electrically conductive traces and providing openings in the solder resist layer, the openings exposing additional metal regions;
- forming a metal surface finish by electrolytically plating metal on the additional metal regions in the openings in the solder resist layer, wherein the core is coupled to a power supply during the electrolytic plating of the metal on the additional metal regions in the openings and delivers current to the additional metal regions;
- removing the core after the electrolytic plating of the metal on the additional metal regions;
- and
- prior to the forming the metal surface finish, forming a protective layer over at least one of the openings in the solder resist layer, wherein the protective layer is formed from a material that will not be plated with metal during an electrolytic plating process.
9 more elements
Dependencies are inferred from the claim text.