Integrated circuit having an edge passivation and oxidation resistant layer and method
AssigneeInfineon Technologies Austria AG
InventorGerhard Schmidt
Life of this patent
Estimating the term…
Abstract
The Examiner objected to the abstract of the disclosure because it contains the phrase “comprising.” The Abstract does not include the phrase “comprising,” however, please amend the abstract as follows: An integrated circuit having a semiconductor component arrangement and production method is disclosed. The integrated circuit as described includes an oxide layer region is provided as a protection against oxidation in the edge region on the surface region of an underlying semiconductor material region.
Claims39
An integrated circuit comprising:
- a semiconductor material having a surface, wherein the semiconductor material is subdivided laterally into a central region and an edge region;
- an arrangement of one or more semiconductor components that is formed in the central region of the semiconductor material;
- a planar passivation layer that is formed on the surface in the edge region, the passivation layer comprising a planar bottom surface, wherein an entirety of the planar bottom surface is in direct contact with the surface of the semiconductor material;
- two or more channel stopper zones that are connected via connections and that are formed in the edge region;
- and
- an oxide layer that is provided on the surface of the semiconductor material in the edge region, the oxide layer being separate from the passivation layer, wherein the oxide layer is formed above and in contact with the two or more channel stopper zones and is adjacent to the passivation layer with only one of the connections in between regions and directly follows the passivation layer.
A method for producing an integrated circuit, comprising:
- forming a semiconductor material having a surface, wherein the semiconductor material is subdivided laterally into a central region and an edge region;
- forming an arrangement of one or more semiconductor components in the central region of the semiconductor material;
- forming a planar passivation layer on the surface of the semiconductor material in the edge region thereof, wherein the passivation layer comprises a planar bottom surface and an entirety of the planar bottom surface is in direct contact with the surface of the semiconductor material;
- providing an oxide layer on the surface of the semiconductor material in the edge region separate from the passivation layer;
- and
- forming a channel stopper region comprising two or more doping zones, wherein the two or more doping zones have a first conductivity type and are formed in the edge region of the surface of the semiconductor material and are connected via connections,
- wherein the oxide layer is adjacent to the passivation layer with only one of the connections in between.
An integrated circuit comprising:
- a semiconductor material having a surface, wherein the semiconductor material is subdivided laterally into a central region and an edge region;
- an arrangement of one or more semiconductor components that is formed in the central region of the semiconductor material;
- a planar passivation layer that is formed on the surface of the semiconductor material in the edge region, the passivation layer comprising a planar bottom surface, wherein an entirety of the planar bottom surface is in direct contact with the surface of the semiconductor material;
- one or more channel stopper zones that are connected via connections and that are formed in the edge region;
- and
- an oxide layer that is provided on the surface of the semiconductor material in the edge region separate from the passivation layer, wherein the oxide layer is formed above and in contact with the one or more channel stopper regions, wherein the oxide layer or a part of the oxide layer is formed in an outer edge region of the edge of the semiconductor material, the outer edge region being spaced apart and remote from the central region, and wherein the oxide layer is adjacent to the passivation layer with only one of the connections in between.
Dependencies are inferred from the claim text.