Monolithically integrated silicon and III-V electronics

A method of forming a monolithically integrated semiconductor device structure, the method comprising:

• providing a silicon substrate;
• disposing a first semiconductor layer over the silicon substrate, wherein the first semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon;
• disposing an insulating layer over the first semiconductor layer in a first region;
• disposing a silicon layer over the insulating layer in the first region;
• forming at least one silicon-based electronic device comprising an element including at least a portion of the silicon layer;
• disposing a second semiconductor layer over at least a portion of the first semiconductor layer in a second region and absent from the first region, wherein the second semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon;
• and
• forming at least one III-V electronic device comprising an element including at least a portion of the second semiconductor layer,
• wherein a top surface of the second semiconductor layer is coplanar with a top surface of the silicon layer.

A monolithically integrated semiconductor device structure comprising:

• a silicon substrate;
• a first semiconductor layer disposed over the silicon substrate, wherein the first semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon;
• a silicon layer disposed over the first semiconductor layer in the first region;
• at least one silicon-based electronic device comprising an element including at least a portion of the silicon layer;
• a second semiconductor layer disposed over at least a portion of the first semiconductor layer in a second region and absent from the first region, wherein the second semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon;
• and
• at least one III-V electronic device comprising an element including at least a portion of the second semiconductor layer,
• wherein a top surface of the second semiconductor layer is coplanar with a top surface of the silicon layer.