Clock-forwarding technique for high-speed links

A system, comprising a link that includes a first signal line, a repeater circuit, and a second signal line, wherein the repeater circuit includes:

• a first input node, coupled to the first signal line, configured to receive a forwarded clock signal;
• a clock multiplier unit (CMU), coupled to the first input node, configured to generate an internal clock signal based at least on the forwarded clock signal;
• a phase interpolator (PI), coupled to the first input node and the CMU, configured to provide an output clock signal based on the forwarded clock signal and the internal clock signal, wherein the CMU and the PI filter cycle-to-cycle jitter in the forwarded clock signal and the internal clock signal;
• and wherein the output clock signal has a phase that is a weighted average of the phases of the forwarded clock signal and the internal clock signal;
• and
• a first output node, coupled to the PI and the second signal line, configured to provide the output clock signal.

A method for providing an output clock signal using a repeater circuit, comprising:

• receiving a forwarded clock signal from a first signal line at a first input node of the repeater circuit;
• generating an internal clock signal based at least on the forwarded clock signal using a CMU in the repeater circuit;
• providing an output clock signal based on the forwarded clock signal and the internal clock signal using a PI in the repeater circuit, wherein the CMU and the PI filter cycle-to-cycle jitter in the forwarded clock signal and the internal clock signal, and wherein the output clock signal has a phase that is a weighted average of the phases of the forwarded clock signal and the internal clock signal;
• and
• providing the output clock signal to a second signal line from a first output node of the repeater circuit.