Mismatch-immune digital-to-analog converter
AssigneeSilicon Laboratories Inc.
InventorJoao Pedro Santos Cabrita Marques
Life of this patent
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Abstract
In an embodiment, a digital-to-analog converter (DAC) includes inputs for receiving first and second signals encoded as a digital signal pair including overlapping low value portions that are substantially equal in duration to overlapping high value portions, within a frame. The DAC further includes an output terminal for providing an analog signal and includes first and second switches responsive to the first and second signals alter a level of the analog signal based on values of the first and second signals to provide a mismatch-immune DAC functionality. In one instance, the switches couple current sources to a common node. In another instance, the switches configure a resistive network to alter a resistance at an input to an amplifier.
Claims20
A digital-to-analog converter (DAC) comprising:
- inputs for receiving first and second signals encoded as a digital signal pair that, within a frame, include overlapping low value portions that are substantially equal in duration to overlapping high value portions;
- an output terminal for providing an analog signal;
- a first current source;
- a second current source;
- a first switch including a control input for receiving the first signal, the first switch configured to selectively couple the first current source to one of ground and the output terminal based on a value of the first signal;
- and
- a second switch including a control input for receiving the second signal, the second switch configured to couple the second current source to one of ground and the output terminal based on a value of the second signal;
- and
- a third current source coupled to the output terminal for providing a bias current.
A digital-to-analog converter (DAC) comprising:
- a differential amplifier including a non-inverting input coupled to ground, an inverting input, and an output for providing an analog signal;
- a feedback resistor having a first terminal coupled to the output and a second terminal coupled to the inverting input;
- a bias resistor having a first terminal coupled to a positive supply terminal and a second terminal coupled to the inverting input;
- first and second inputs for receiving first and second signals, respectively, the first and second signals comprising an encoded signal pair including overlapping low value portions that are substantially equal in duration to overlapping high value portions within a frame;
- a resistive network including a plurality of resistors and a respective plurality of switches, each resistor including a first terminal coupled to the inverting input and a second terminal coupled to a corresponding one of the respective plurality of switches, each switch responsive to one of the first and second signals to selectively couple the corresponding resistor to one of the positive supply terminal and a negative supply terminal to alter a voltage applied to the inverting input.
A method of providing an analog output signal, the method comprising:
- receiving first and second signals having overlapping low value portions that are substantially equal in duration to overlapping high value portions within a frame;
- applying the first signal to a control terminal of a first switch and the second signal to a control terminal of a second switch to alter a current provided to a common node;
- and
- providing the current into the common node to an output terminal as the analog output signal.
Dependencies are inferred from the claim text.