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US 8,115,246 B2Granted
Semiconductor device including protrusion type isolation layer
AssigneeSamsung Electronics Co., Ltd.
InventorsDong-hyun Kim, Jai-kyun Park
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Abstract
A semiconductor device may include a semiconductor layer having a convex portion and a concave portion surrounding the convex portion. The semiconductor device may further include a protrusion type isolation layer filling the concave portion and extending upward so that an uppermost surface of the isolation layer is a at level higher that an uppermost surface of the convex portion.
Claims19
A semiconductor device, comprising:
- a semiconductor layer including a convex portion and a concave portion surrounding the convex portion;
- a protrusion type isolation layer filling the concave portion and extending upward so that an uppermost surface of the isolation layer is at a level higher than an uppermost surface of the convex portion;
- at least one trench in the convex portion;
- at least one gate structure in the at least one trench, the at least one gate structure having a gate insulating layer and a gate conductive layer that are buried in the semiconductor layer, and an uppermost surface of the at least one gate structure being at a level lower than the uppermost surface of the isolation layer;
- and
- a contact plug on and electrically connected to a source/drain region of the convex portion, the contact plug being surrounded by the isolation layer.
3 more elements
A semiconductor device, comprising:
- a semiconductor layer including a convex portion and a concave portion surrounding the convex portion;
- a protrusion type isolation layer filling the concave portion and extending upward so that an uppermost surface of the isolation layer is at a level higher that an uppermost surface of the convex portion;
- at least one trench in the convex portion;
- and
- at least one gate structure in the at least one trench, the at least one gate structure having a gate insulating layer and a gate conductive layer that are buried in the semiconductor layer, and an uppermost surface of the at least one gate structure being at a level lower than the uppermost surface of the isolation layer.
2 more elements
Dependencies are inferred from the claim text.