Process and method for a decoupled multi-parameter run-to-run controller

A process of forming an integrated circuit, comprising the steps:

• providing a first semiconductor substrate of a first integrated circuit design;
• providing a parameter target value for said integrated circuit;
• providing a first semiconductor processing tool;
• computing a first tool setting for said first semiconductor processing tool, such that said first tool setting includes a first tool offset divided by a first tool process factor, and a first integrated circuit design offset value divided by said first tool process factor;
• performing a fabrication step on said first semiconductor substrate using said first semiconductor processing tool at said first tool setting;
• measuring an integrated parameter value of said integrated circuit after said fabrication step is performed;
• computing an error value, said error value being a difference between said measured integrated circuit parameter value and said parameter target value;
• generating a value for a tool weight;
• generating a value for a device weight, such that exactly one of said tool weight and said device weight is assigned a non-interference value;
• generating an updated tool offset by adjusting a current tool offset of said first semiconductor processing tool by a product of said tool weight and a sum of said error value and a difference between said first tool offset and said current tool offset;
• generating an updated integrated circuit design offset of said first integrated circuit design by adjusting a current integrated circuit design offset of said first integrated circuit design by a product of said device weight and a sum of said error value and a difference between said first integrated circuit design offset and said current integrated circuit design offset;
• providing a second semiconductor substrate;
• and
• performing said fabrication step on said second semiconductor substrate using said first semiconductor processing tool or a second semiconductor processing tool at an updated tool setting, said updated tool setting using at least one of said updated tool offset and said updated integrated circuit design offset, wherein if said first semiconductor processing tool is used, said second semiconductor substrate is of said first integrated circuit design or a second integrated circuit design, and if said second semiconductor processing tool is used, said second semiconductor substrate is of said first integrated circuit design.