US 8,110,501 B2Granted

Method of fabricating landing plug with varied doping concentration in semiconductor device

AssigneeHynix Semiconductor Inc.

InventorKyoung Bong Rouh

Life of this patent

Estimating the term…

Loading patent…

Abstract

A method of fabricating a landing plug in a semiconductor memory device, which in one embodiment includes forming a landing plug contact hole on a semiconductor substrate having an impurity region to expose the impurity region; forming a landing plug by filling the landing plug contact hole with a polysilicon layer, wherein the landing plug is divided into a first region, a second region, a third region, and a fourth region from a lower portion of the landing plug, and the first region is doped with a first doping concentration that is relatively lowest, the second region is doped with a second doping concentration that is higher than the first doping concentration, the third region is doped with a third doping concentration that is higher than the second doping concentration and the fourth region is not doped; and annealing the resulting product formed with the landing plug.

Claims6

Dependent claims

A method of fabricating a landing plug in a semiconductor memory device, comprising:

forming a landing plug contact hole on a semiconductor substrate having an impurity region to expose the impurity region;
forming a landing plug by filling the landing plug contact hole with a polysilicon layer, wherein the landing plug comprises a first region, a second region, a third region, and a fourth region, with the first region being disposed between the substrate and the second region and having a first doping concentration, the second region being disposed over the first region and under the third region and having a second doping concentration that is higher than the first doping concentration, the third region being disposed over the second region and under the fourth region and having a third doping concentration that is higher than the second doping concentration, and the fourth region being disposed over the third region and not being doped;
and
annealing the resulting product formed with the landing plug.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 12/822,461Filed 24 Jun 2010
Priority: KR 10-2009-005762926 Jun 2009
Published: US 2010/0330801 A130 Dec 2010
Granted: 7 Feb 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10W 20/0698
Of conductive parts of the interconnections: local interconnections
H10B 12/0335
The capacitor extending over the transistor: making a connection between the transistor and the capacitor, e.g. plug
H10D 64/0113
To Group IV semiconductors: the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers
H10P 14/43
Using a gas or vapour: chemical deposition, e.g. chemical vapour deposition [CVD]