Cache memory and a method for servicing access requests
AssigneeFreescale Semiconductor, Inc.
InventorsShai Koren, Alon Eldar, Amit Gur, Itay Peled, Rotem Porat
Life of this patent
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Abstract
A cache memory that includes: (i) an arbitrator, connected to multiple access generator, the arbitrator is adapted to receive different types of access requests from the multiple access generators and to select a single access request per arbitration cycle; (ii) a sequence of pipeline stages, the sequence comprises an input pipeline stage that is connected to the arbiter; and (iii) multiple cache resources, connected to the sequence of pipeline stages; wherein each cache resource can be read only by a small portion of the sequence of pipeline stages and can be written to only by a small portion of the sequence of pipeline stages.
Claims17
A cache memory, comprising:
- an arbitrator, coupled to multiple access generators, the arbitrator is adapted to receive different types of access requests from the multiple access generators and to select a single access request per arbitration cycle;
- a plurality of sequential pipeline stages, wherein the plurality of sequential pipeline stages comprises an input pipeline stage that is coupled to the arbiter, and wherein each pipeline stage of the plurality of sequential pipeline stages is associated with a type of access request;
- and
- multiple cache resources, each cache resource coupled to one or more pipeline stage of the plurality of sequential pipeline stages;
- wherein a particular cache resource can be read by a first pipeline stage of the plurality of sequential pipeline stages and can be written to by a second pipeline stage of the plurality of sequential pipeline stages.
A method for servicing access requests, the method comprises:
- arbitrating, by an arbitrator, between different types of access requests from multiple access generators;
- providing a selected access request to access a cache memory resource to a plurality of sequential pipeline stages, wherein:
- each pipeline stage of the plurality of sequential pipeline stages is associated with a type of access request;
- and
- the plurality of sequential pipeline stages comprises an input pipeline stage that is coupled to the arbiter;
- and
- processing the selected access request by the plurality of sequential pipeline stages, wherein:
- the processing comprises accessing one or more cache resources;
- and
- a particular cache resource can be read by a first pipeline stage of the sequence of pipeline stages and can be written to by a second pipeline stage of the plurality of sequential pipeline stages.
A method for designing a cache memory, the method comprising:
- receiving a request to update a design of a cache memory such as to support a new access type, wherein:
- the cache memory is adapted to support certain access types and comprises multiple cache resources and an arbitrator that is coupled to multiple access generators;
- the arbitrator is adapted to receive certain types of access requests from the multiple access generators and to select a single access request per arbitration cycle;
- the arbitrator is further coupled to an input pipeline stage of a plurality of sequential pipeline stages;
- and
- each pipeline stage of the plurality of sequential pipeline stages is associated with a type of access request;
- and
- a particular cache resource can be read by a first pipeline stage of the plurality of sequential pipeline stages and can be written to by a second pipeline stage of the plurality of sequential pipeline stages.
Dependencies are inferred from the claim text.