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US 8,102,292 B1Granted
Analog-to-digital converter (ADC) having a successive-approximation register digital to-analog converter (SARDAC)
AssigneeCypress Semiconductor Corporation
InventorDavid Van Ess
Life of this patent
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Abstract
An analog-to-digital converter (ADC) having a successive-approximation register digital-to-analog converter (SARDAC) is described.
Claims19
A circuit, comprising:
- an analog-to-digital converter (ADC), comprising:
- a comparator to receive an input voltage at a first input terminal;
- logic circuitry coupled to the output of the comparator, wherein the logic circuitry is configured to provide a digital output at a first output terminal of the ADC;
- and
- a digital-to-analog converter (DAC) coupled to receive the digital output of the logic circuitry, wherein the DAC is configured to convert the digital output into an analog output, feedback the analog output into a second input terminal of the comparator, and provide the analog output at a second output terminal of the ADC;
- and
- a sample and hold circuit coupled to receive the analog output from the second output terminal of the ADC, wherein the sample and hold circuit is configured to sample and hold the analog output as a feedback signal and provide the feedback signal to a first difference circuit.
4 more elements
An apparatus, comprising:
- a delta sigma analog-to-digital converter (ADC) to receive an input voltage and to provide a digital output value corresponding to the input voltage, wherein the delta sigma ADC uses a delta sigma feedback and comprises a digital-to-analog converter (DAC);
- and
- means for providing the delta sigma feedback without an additional delta sigma feedback DAC;
- and
- means for dynamically reconfiguring the delta sigma ADC between a high-speed ADC in a first programmable mode and a lower-speed ADC in a second programmable mode, wherein the lower-speed ADC has a higher resolution than the high-speed ADC.
2 more elements
A method, comprising:
- receiving an input voltage at an input terminal of a Successive-approximation Register DAC (SARDAC), the SARDAC comprising an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC);
- converting the input voltage into a digital output using the ADC;
- converting the digital output into an analog output using the DAC;
- providing the analog output as feedback to the ADC;
- providing the digital output at a first output terminal of the SARDAC and the analog output at a second output terminal of the SARDAC;
- sampling and holding the analog output at the second output terminal as a feedback signal;
- calculating a difference between an input signal and the feedback signal;
- and
- integrating the difference to generate the input voltage at the input terminal of the SARDAC.
6 more elements
A method, comprising:
- receiving an input voltage at an input terminal of a Successive-approximation Register DAC (SARDAC), the SARDAC comprising a digital-to-analog converter (DAC);
- converting the input voltage into a digital output;
- converting the digital output into an analog output using the DAC;
- providing the digital output at a first output terminal of the SARDAC and the analog output at a second output terminal of the SARDAC;
- and
- dynamically reconfiguring the SARDAC to be used in a high-speed analog-to-digital converter (ADC) in a first programmable mode and as a lower-speed ADC in a second programmable mode, wherein the lower-speed ADC has a higher resolution than the high-speed ADC.
3 more elements
Dependencies are inferred from the claim text.