Blind adaptive decision feedback equalizer for high-speed serial communications

A blind adaptive decision feedback equalizer method for filtering an analog input data signal to provide a decided digital data output, said method comprising:

• storing a first plurality of previous decided digital data samples;
• summing said analog input data signal with a number of terms, equal to said first plurality, each derived from one of said previous decided digital data samples, to produce a filtered analog input data signal;
• and
• digitizing said filtered analog input data signal to produce said decided digital data output;
• wherein:
• each of said terms is derived by multiplying each respective stored previously decided digital data sample by a respective coefficient determined by:
• applying an error generation function to said filtered analog input data signal to provide an assigned error value to said filtered analog input data signal,
• applying said assigned error value and said respective stored previously decided digital data sample to respective adaptation logic to generate a respective coefficient update,
• accumulating said respective coefficient updates during a predetermined number of clock cycles, and
• outputting said accumulated respective coefficient updates only after a second plurality of respective updates has occurred.

An equalization method for filtering an input signal, said method comprising:

• assigning a first error value to a positive input signal having a magnitude less than a first threshold;
• assigning a second error value to a negative input signal having a magnitude less than said first threshold;
• assigning a third error value to an input signal having a magnitude at least equal to said first threshold;
• applying said assigned error value to adaptation logic to generate a coefficient update;
• accumulating respective coefficient updates during a predetermined number of clock cycles;
• and
• outputting said accumulated respective coefficient updates only after a predetermined plurality of respective updates has occurred.

A blind adaptive decision feedback equalizer that filters an analog input data signal to provide a decided digital data output, said blind adaptive decision feedback equalizer comprising:

• memory that stores a first plurality of previous decided digital data samples;
• a summing node that sums said analog input data signal with a number of terms, equal to said first plurality, each derived from one of said previous decided digital data samples, to produce a filtered analog input data signal;
• a converter that digitizes said filtered analog input data signal to produce said decided digital data output;
• and
• circuitry for deriving said terms, said circuitry comprising:
• a respective multiplier that multiplies each respective stored previously decided digital data sample by a respective coefficient,
• an error generator that assigns (a) a first error value to a positive filtered analog input data signal having a magnitude less than a first threshold, (b) a second error value to a negative filtered analog input data signal having a magnitude less than said first threshold, and (c) a third error value to a filtered analog input data signal having a magnitude at least equal to said first threshold, and
• adaptation logic that acts on said assigned error value and said respective stored previously decided digital data sample to generate a respective coefficient update, each respective coefficient update being outputted to said respective coefficient.

A blind adaptive decision feedback equalizer that filters an analog input data signal to provide a decided digital data output, said blind adaptive decision feedback equalizer comprising:

• memory that stores a first plurality of previous decided digital data samples;
• a summing node that sums said analog input data signal with a number of terms, equal to said first plurality, each derived from one of said previous decided digital data samples, to produce a filtered analog input data signal;
• a converter that digitizes said filtered analog input data signal to produce said decided digital data output;
• and
• circuitry for deriving said terms, said circuitry comprising:
• a respective multiplier that multiplies each respective stored previously decided digital data sample by a respective coefficient,
• an error generator that assigns error value to said filtered analog input data signal,
• adaptation logic that acts on said assigned error value and said respective stored previously decided digital data sample to generate a respective coefficient update, each respective coefficient update being outputted to said respective coefficient,
• registers for accumulating said respective coefficient updates during a predetermined number of clock cycles, and
• counters for controlling output of said accumulated respective coefficient updates only after a second plurality of respective updates has occurred.