Error correction method with instruction level rollback

An error correction method for an information processing unit, which comprises a CPU with pipeline structure and a rollback control unit connected to the CPU via a bus, said method comprising:

• when an error is detected, restoring a content of a register file from a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error;
• and
• re-executing an instruction from an [Instruction N+1] which is the next instruction after the [Instruction N]
• wherein:
• the CPU includes a plurality of first flip flops, a parity check circuit and a second flip flop,
• the rollback control unit include an error mask circuit,
• the error mask circuit includes a plurality of mask logistics,
• wherein output signals of the plurality of first flip flops are input to the parity check circuit, the parity check circuit inputs a signal obtained by collecting parity check results of each output signal by logical add to the second flip flop, and the second flip flop outputs an error detection signal, and
• when the error detection signal is a predetermined value, the plurality of mask logics make an address, an instruction code, a write control and a write data into invalid values.

An information processing unit for performing an error correction method, comprising:

• a CPU with pipeline structure;
• and
• a rollback control unit connected to the CPU via a bus which, when an error is detected, restores a content of a register file from a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error and re-executes an instruction from an [Instruction N+1] which is the next instruction after the [Instruction N],
• wherein:
• the CPU includes a plurality of first flip flops, a parity check circuit and a second flip flop,
• the rollback control unit includes an error mask circuit,
• the error mask circuit includes a plurality of mask logics,
• output signals of the plurality of first flip flops are input to the parity check circuit, the parity check circuit inputs a signal obtained by collecting parity check results of each output signal by logical add to the second flip flop, and the second flip flop outputs an error detection signal, and
• when the error detection signal is a predetermined value, the plurality of mask logics make an address, an instruction code, a write control and a write data into invalid values.

An information processing unit for performing an error correction method, comprising:

• a CPU with pipeline structure;
• and
• a rollback control unit connected to the CPU via a bus, which, when an error is detected, restores a content of a register file from a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error and re-executes an instruction from an [Instruction N+1] which is the next instruction after the [Instruction N],
• wherein:
• the rollback control unit includes a CPU bus error detector which detects an error of a CPU bus write accompanied with execution of an instruction subsequent to the error occurrence,
• the CPU bus error detector has a plurality of comparators, and
• read data from the delayed register file and address data on the CPU bus are compared by the plurality of comparators and a bus write cancel is issued based on the comparison result.