Integration of non-volatile charge trap memory devices and logic CMOS devices

A method of fabricating a semiconductor structure, the method comprising:

• implanting a first dopant species into a first region of a semiconductor substrate to form an n-well for a PMOS transistor;
• forming a non-volatile charge trapping dielectric stack over a second region of the semiconductor substrate after forming the PMOS transistor n-well, the non-volatile charge trapping dielectric stack including a blocking layer on a charge trapping layer over a tunneling layer formed on the semiconductor substrate;
• forming a gate oxide of the PMOS transistor over the first region of the semiconductor substrate after forming the non-volatile charge trapping dielectric stack;
• forming a PMOS gate stack and another MOS gate stack over the first region of the semiconductor substrate;
• forming a first sidewall spacer adjacent to the PMOS gate stack and a second sidewall spacer adjacent to the another MOS gate stack;
• implanting a source and drain into the first region adjacent to the first sidewall spacer prior to depositing a multi-layer liner;
• depositing the multi-layer liner over the second sidewall spacer, the multi-layer liner including a top layer and a bottom layer;
• etching the top layer selective to the bottom layer to form a disposable sidewall spacer separated from the second sidewall spacer by at least the bottom layer;
• implanting a source and a drain offset from the second sidewall spacer by the disposable sidewall spacer to increase a breakdown voltage;
• removing the disposable sidewall spacer selectively to the bottom layer;
• and
• forming silicide over the first region of the semiconductor substrate while blocking formation of silicide over the non-volatile charge trapping dielectric stack.