Thyristor semiconductor memory and method of manufacture

A method of fabricating a thyristor-based semiconductor device, comprising:

• forming a first well, a second well and a third well in a thyristor region within a semiconductor substrate;
• wherein the first well is formed above the second well;
• wherein the second well is formed above the third well;
• wherein the second well is a completely buried well;
• wherein the third well is located below the second well;
• wherein the first well and the third well have a first-type conductivity;
• wherein the second well has a second-type conductivity different from the first-type conductivity;
• forming isolation trenches in the semiconductor substrate of a p/n-type conductivity, to define at least in part a lateral extent to an active region of the semiconductor substrate;
• forming the second well within the active region of the semiconductor substrate, the second well formed with an n/p-type conductivity and depth less than that of the isolation trenches;
• forming a control gate in an insulated, capacitively-coupled relationship over a p/n-base region for the thyristor within the active region, wherein the p/n-base region is defined at least in part between the second well and the a top surface of the semiconductor substrate over which the control gate is disposed;
• forming an n/p-base region for the thyristor within the active region of the semiconductor substrate with an inverted “T” structure, defined at least in part by the second well, wherein a stem for the inverted “T” structure is formed with the n/p-type conductivity that joins the second well to incorporate the second well operably as a portion of the n/p base region;
• forming an anode/cathode region within the active region to border a side of the stem opposite the p/n-base;
• forming a cathode/anode region within the active region of semiconductor substrate in self-aligned relationship with respect to a shoulder of the control gate distal the anode/cathode region for the thyristor, wherein the cathode/anode region is formed with depth sufficiently shallow to define a thinned portion of the p/n-base region between the cathode/anode region and the second well;
• forming MOSFET devices for electrical integration with and during fabrication of the thyristor;
• wherein a first dielectric layer, a second dielectric layer, and a third dielectric layer are conformally formed and etched to define extension spacers against a gate of the MOSFET;
• wherein the first dielectric layer, the second dielectric layer, and the third dielectric layer are similarly conformally layered over the semiconductor substrate of the active region for the thyristor;
• and
• portions of the conformally layered dielectric is kept over and against the active region for preserving an integrity at the top surface of the semiconductor substrate therefor during masking and implanting processes associated with forming the at least one of (i) the stem to the n/p-base, (ii) the anode/cathode region, and (iii) the cathode/anode region.