Solid state drive power safe wear-leveling

#In a variety of consumer electronics, solid state drives are more and more frequently replacing conventional rotating hard disk drives for mass storage. These solid state drives may include one or more flash memory devices, the flash memory devices may be logically divided into blocks, and each of the blocks may be further logically divided into addressable pages. These addressable pages may be any of a variety of sizes (e.g., 512 Byte, 1 Kilobyte, 2 Kilobytes, 4 Kilobytes), which may or may not match the logical block address sizes used by a host computing device.

#During a write operation, data may be written to the individual addressable pages in a block of a flash memory device. However, in order to erase or rewrite a page, an entire block must typically be erased. Of course, different blocks in each flash memory device may be erased more or less frequently depending upon the data stored therein. Thus, since the lifetime of storage cells of a flash memory device correlates with the number of erase cycles, many solid state drives perform wear-leveling operations (both static and dynamic) in order to spread erasures more evenly over all of the blocks of a flash memory device.

#During a static wear-leveling operation, data in a source block that has been relatively infrequently erased may be moved to a target block, such that new data may be recorded to the source block, which may then be erased more frequently. Unfortunately, in conventional solid state drives, if power is lost during the static wear-leveling operation, data being moved from the source block to the target block may be lost. In some solid state drives, this data loss may be unrecoverable. In other solid state drives, the data may remain in the source block, but the entire move operation must be started from the beginning if the solid state drive experiences a power failure.

#FIG. 1 is a schematic view generally illustrating an example solid state drive incorporating a plurality of flash memory devices, according to one illustrated embodiment.

#FIG. 2 is a schematic view illustrating another example solid state drive incorporating a single flash memory device, according to one illustrated embodiment.

#FIG. 3 is a schematic view illustrating an example solid state drive within a computing device, according to one illustrated embodiment.

#Referring to FIG. 1, according to one embodiment, solid state drive (SSD) 1 comprises a first flash memory device 2a, a second flash memory device 2b and a memory controller 4 coupled to the first flash memory device 2a and the second flash memory device 2b. The first flash memory device 2a is logically divided into a first plurality of blocks 60-j (collectively 6, illustrated as horizontal rows), each of the first plurality of blocks 6 being logically divided into addressable pages 80-k (collectively 8, delineated by the vertical lines running through the rows). Similarly, the second flash memory device 2b is logically divided into a second plurality of blocks 100-j (collectively 10, illustrated as horizontal rows), each of the second plurality of blocks 10 being logically divided into addressable pages 120-k (collectively 12, delineated by the vertical lines running through the rows). The memory controller 4 may be configured to logically associate a first block (e.g., block 60) of the first plurality of blocks 6 with a second block (e.g., block 100) of the second plurality of blocks 10 to form a first zip code, the first zip code associated with a first erase counter. The memory controller 4 may be further configured to logically associate a first source block (e.g., block 61) of the first plurality of blocks 6 with a second source block (e.g., block 101) of the second plurality of blocks 10 to form a second zip code, the second zip code associated with a second erase counter. The SSD 1 further comprises a processor 14 coupled to the memory controller 4 and operable to execute instructions, and a computer-readable memory 16 having instructions stored thereon that are executable by the processor 14 in order to cause the processor 14 to perform a wear-leveling operation, by: determining that the first block 60 and the second block 100 in the first zip code have been erased; based at least in part on the determination, incrementing the first erase counter associated with the first zip code; after incrementing the first erase counter, determining that the second erase counter associated with the second zip code is low relative to at least one other erase counter; and based at least in part on determining that the second erase counter is low, writing data from the first source block 61 and the second source block 101 in the second zip code to a first target block (e.g., block 62) of the first plurality of blocks 6 and a second target block (e.g., block 102) of the second plurality of blocks 10 as part of the wear-leveling operation.

#As illustrated herein, the SSD 1 comprises a drive including N flash memory devices 2 coupled to a single memory controller 4. In one embodiment, the solid state drive 1 may include just two flash memory devices 2a, b. In other embodiments, the solid state drive 1 may include three or more flash memory devices 2, as illustrated.

#The flash memory devices 2 may comprise any of a variety of types of Electrically Erasable Programmable Read-Only Memory (EEPROM) flash memory. In one embodiment, each flash memory device 2 comprises NAND multi-level cell (MLC) flash. In another embodiment, NOR and/or single-level cell (SLC) flash memory devices may be used. Each flash memory device 2 may include a distinct input/output port (not illustrated) configured to send and receive user data to and from the memory controller 4. In some embodiments, the flash memory devices 2 may support internal data copies, such that circuitry within the flash memory devices 2 is operable to copy data from one page to another without sending and receiving data via its I/O port. However, in other embodiments, the flash memory devices 2 may not support such functionality.