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US 8,090,897 B2Granted
System and method for simulating an aspect of a memory circuit
AssigneeGoogle Inc.
InventorsSuresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
Life of this patent
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Abstract
A memory subsystem is provided including an interface circuit adapted for coupling with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. Such aspect includes a signal, a capacity, a timing, and/or a logical interface.
Claims20
A sub-system, comprising:
- an interface circuit operable for receiving, from a system, write data to be stored on a first memory circuit and for communicating the write data to the first memory circuit, the first memory circuit having a first latency for the write data,
- wherein the interface circuit is further operable to:
- cause the first memory circuit to appear to the system as a second memory circuit having a second latency for the write data, the second latency being different than the first latency;
- and
- time shift communication of the write data to the first memory circuit by an amount of time equal to a difference between the first latency and the second latency, where the difference between the first latency and the second latency is equal to or greater than one clock cycle, and where the first latency includes at least one of a first row address strobe to column address strobe latency (tRCD), a first row precharge latency (tRP), a first activate to precharge latency (tRAS), or a first row cycle time (tRC), and the second latency includes at least one of a second tRCD, a second tRP, a second tRAS, or a second tRC.
2 more elements
A system, comprising:
- a first memory circuit;
- and
- an interface circuit in communication with the first memory circuit and a system device, the interface circuit operable to receive, from the system device, write data to be stored on the first memory circuit,
- wherein the first memory circuit has a first latency for the write data, and
- the interface circuit is further operable to:
- cause the first memory circuit to appear to the system device as a second memory circuit having a second latency for the write data, the second latency being different than the first latency;
- and
- time shift communication of the write data to the first memory circuit by an amount of time equal to a difference between the first latency and the second latency, where the difference between the first latency and the second latency is equal to or greater than one clock cycle, and where the first latency includes at least one of a first row address strobe to column address strobe latency (tRCD), a first row precharge latency (tRP), a first activate to precharge latency (tRAS), or a first row cycle time (tRC), and the second latency includes at least one of a second tRCD, a second tRP, a second tRAS, or a second tRC.
5 more elements
Dependencies are inferred from the claim text.