US 8,089,103 B2Granted

Integrated circuit device with gate level region including at least three linear-shaped conductive segments having offset line ends and forming three transistors of first type and one transistor of second type

AssigneeTela Innovations, Inc.

InventorsScott T. Becker, Michael C. Smayling

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. A gate electrode level region is formed above the substrate portion to include conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a substantially equal and minimum size across the gate electrode level region. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication. Some of the conductive features extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the gate electrode level region is greater than or equal to eight.

Claims34

Dependent claims

An integrated circuit, comprising:

a gate electrode level region including at least three linear-shaped conductive segments formed to extend lengthwise in a first direction, the at least three linear-shaped conductive segments including:
a first linear-shaped conductive segment that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type,
a second linear-shaped conductive segment that forms a gate electrode of a second transistor of the first transistor type, and
a third linear-shaped conductive segment that forms a gate electrode of a third transistor of the first transistor type,
wherein at least one end of the second linear-shaped conductive segment is offset in the first direction relative to any end of the first and third linear-shaped conductive segments, and
wherein at least one end of the third linear-shaped conductive segment is offset in the first direction relative to any end of the first and second linear-shaped conductive segments.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/567,609Filed 25 Sep 2009 · continuation
Priority: 9 Mar 2006
Published: US 2010/0032723 A111 Feb 2010
Granted: 3 Jan 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification26 codes

H10D 84/907
Comprising field effect technology: cMOS gate arrays
G06F 30/39
Circuit design: circuit design at the physical level
G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
H10D 64/01326
Characterised by the conductor: aspects related to lithography, isolation or planarisation of the conductor

Family

Application60/781,288Us provisional application · filed 9 Mar 2006
Application11/683,402Parent of this continuation · filed 7 Mar 2007
Application12/212,562Parent of this continuation · filed 17 Sep 2008
US 2010/0032723 A1Pre-grant publication · published 11 Feb 2010
US 7,842,975 B2Parent of this continuation
US 7,446,352 B2Parent of this continuation
US 2007/0210391 A1Published application
US 2009/0014811 A1Published application
US 8,089,103 B2This patent

From the US filing history. Foreign family members aren’t listed.