Integrated circuit device and associated layout including gate electrode level region of 965 NM radius with linear-shaped conductive segments on fixed pitch

An integrated circuit, comprising:

• a substrate;
• and
• a gate electrode level region that forms part of a gate electrode level of the integrated circuit over the substrate, wherein the gate electrode level region corresponds to a circular area of the gate electrode level parallel to the substrate having a radius of up to about 965 nanometers,
• wherein the gate electrode level region includes a first conductive segment that forms both a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type,
• wherein the gate electrode level region includes a second conductive segment that forms a gate electrode of a second transistor of the first transistor type,
• wherein the gate electrode level region includes a third conductive segment that forms a gate electrode of a second transistor of the second transistor type,
• wherein the gate electrode level region includes a fourth conductive segment that forms a gate electrode of a third transistor of the first transistor type,
• wherein the gate electrode level region includes a fifth conductive segment that forms a gate electrode of a third transistor of the second transistor type,
• wherein the gate electrode level region includes a sixth conductive segment that forms both a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type, and
• wherein each conductive segment within the gate electrode level region is linear-shaped and oriented to extend lengthwise in a first direction so as to have a respective centerline that extends in the first direction, and wherein each conductive segment within the gate electrode level region is positioned according to a fixed centerline-to-centerline spacing as measured in a second direction perpendicular to the first direction, and wherein the gate electrode level region includes at least one conductive segment positioned at each of a number of locations corresponding to the fixed centerline-to-centerline spacing.