# US 8,082,044 B2 · Apparatus and methods for precompiling program sequences processing for wafer processing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,082,044 B2 - Document ID: US8082044B2 - Status: Granted - Kind: B2 - Application number: 12/338,781 - Filed: 2008-12-18 - Published: 2009-05-21 - Granted: 2011-12-20 - Earliest claimed: 2006-11-06 - Assignees: Novellus Systems, Inc. - Inventors: Jaideep Jain; Qiang Zhou; Steve Kleinke - Web page: https://patentgrep.com/patent/US8082044B2 ## CPC - G05B 19/4148: {characterised by using several processors for different functions, distributed (real-time) systems (G05B19/4141 takes precedence)} - G05B 2219/33104: Tasks, functions are distributed over different cpu - G05B 2219/45031: Manufacturing semiconductor wafers - G05B: CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS (systems for controlling or regulating non-electric variables G05D; systems for regulating electric or magnetic variables G05F; control devices or systems insofar as characterised by mechanical features only G05G) ## Abstract Disclosed are apparatus and methods for embodiments for efficiently and flexibly controlling hardware devices in a semiconductor processing system are provided for use in a distributed control arrangement. In general, the distributed arrangement includes at least one upper-level controller that is configurable with a computer program sequence of instructions for controlling one or more hardware devices of a processing tool. The hardware devices are controlled through one or more lower-level controllers. Prior to execution of the program sequence of the upper-level controller, at least one instruction of this program is pre-compiled so as to translate the instruction for execution by a selected lower-level controller and to add an at least one interlock check to such pre-compiled instruction and make the translated instruction accessible to at least one lower-level controller. The interlock check specifies one or more condition(s) for the selected lower-level controller to execute the pre-compiled instruction. Any number of instructions of the upper-level controller may be translated for use by any number of selected lower-level controllers, where some of the translated instructions include one or more interlock checks. ## Claims ### Claim 1 A method of controlling a plurality of hardware devices of a semiconductor processing system, the method comprising: a) providing a program sequence for an upper-level controller, wherein the program sequence includes a plurality of instructions for controlling one or more of the hardware devices of the processing system via one or more of a plurality of lower-level controllers; b) translating a selected one of the instructions into a translated set of instructions that is executable by a selected lower-level controller only when a condition of one or more hardware devices of the processing system is met; and c) initiating execution of a process in the processing system based in part on execution of the translated set of instructions by the selected lower-level controller after the condition of one or more hardware devices of the processing system is met. ### Claim 2 (depends on 1) A method as recited in claim 1, wherein the condition specifies that an operational condition of one or more hardware devices of the processing system is met. ### Claim 3 (depends on 2) A method as recited in claim 2, wherein the operational condition specifies that a valve is open. ### Claim 4 (depends on 2) A method as recited in claim 2, wherein the operational condition specifies that a valve is closed. ### Claim 5 (depends on 2) A method as recited in claim 2, wherein the operational condition specifies a predefined flow rate. ### Claim 6 (depends on 1) A method as recited in claim 1, wherein the step of translating includes translating from a first language recognizable by the upper-level controller to a second language recognizable by the selected lower-level controller. ### Claim 7 (depends on 2) A method as recited in claim 2, further comprising: simulating operation of the hardware devices based on simulating execution of the program sequence so as to determine whether the condition of the one or more hardware devices is met; and inhibiting initiation execution of the process when the condition is not met. ### Claim 8 (depends on 2) A method as recited in claim 2, wherein execution of the process includes real time interlock checking to verify whether one or more predefined states of the hardware device(s) meet one or more requirements of the operational condition. ### Claim 9 A system for controlling a plurality of hardware devices of a semiconductor processing system, the system comprising: an upper-level controller comprising one or more processors and one or more memory wherein at least one of the processors and memory of the upper-level controller are adapted for providing a program sequence for the an upper-level controller, wherein the program sequence includes a plurality of instructions for controlling one or more of the hardware devices of the processing system via one or more of a plurality of lower-level controllers and a plurality of lower level controllers coupled with the upper-level controller, each lower-level controller comprising one or more processors and one or more memory, wherein at least one of the processors and memory of each lower-level controller are adapted for executing one or more translated instructions that are made accessible to such each lower-level controller, wherein at least one of the processors and memory of the upper-level controller are further adapted for translating a selected one of the instructions into a translated set of instructions that is executable by a selected one of the lower-level controllers only when a condition of one or more hardware devices of the processing system is met; and initiating execution of a process in the processing system based in part on execution of the translated set of instructions by the selected lower-level controller after the condition of one or more hardware devices of the processing system is met. ### Claim 10 (depends on 9) A system as recited in claim 9, wherein the condition specifies that an operational condition of one or more hardware devices of the processing system is met. ### Claim 11 (depends on 10) A system as recited in claim 10, wherein the operational condition specifies that a valve is open. ### Claim 12 (depends on 10) A system as recited in claim 10, wherein the operational condition specifies that a valve is closed. ### Claim 13 (depends on 10) A system as recited in claim 10, wherein the operational condition specifies a predefined flow rate. ### Claim 14 (depends on 9) A system as recited in claim 9, wherein translating is accomplished by translating from a first language recognizable by the upper-level controller to a second language recognizable by the selected lower-level controller. ### Claim 15 (depends on 12) A system as recited in claim 12, wherein the at least one of the processors and memory of the upper-level controller are further adapted for simulating operation of the hardware devices based on simulating execution of the program sequence so as to determine whether the condition of the one or more hardware devices is met; and inhibiting execution of the process when the condition is not met. ### Claim 16 (depends on 10) A system as recited in claim 10, wherein execution of the process includes real time interlock checking to verify whether one or more predefined states of the hardware device(s) meet one or more requirements of the operational condition. ### Claim 17 A method of controlling a hardware device of a semiconductor processing system, the method comprising: receiving at a lower-level controller a translated set of instructions program and one or more interlock checks from an upper-level controller, wherein the set of instructions are operable to control one or more of the hardware devices of the processing system via the lower-level controller, wherein the interlock specifies an operational condition that is to be met with respect to the one or more hardware devices prior to execution of the translated set of instructions; and initiating execution of a process in the processing system based in part on execution of the translated set of instructions by the lower-level controller after the condition is met. ### Claim 18 (depends on 17) A method as recited in claim 17, further comprising: simulating operation of the hardware devices based on simulating execution of the program sequence while performing the one or more interlock check(s) for each set of translated instructions to determine whether an interlock check fails; and inhibiting execution of the process when an interlock check fails. ### Claim 19 A lower level controller comprising one or more processors and one or more memory, wherein at least one of the processors and memory are adapted for: receiving at the lower-level controller a translated set of instructions program and one or more interlock checks from an upper-level controller, wherein the set of instructions are operable to control one or more of the hardware devices of the processing system via the lower-level controller, wherein the interlock specifies an operational condition that is to be met with respect to the one or more hardware devices prior to execution of the translated set of instructions; and initiating execution of a process in the processing system based in part on execution of the translated set of instructions by the lower-level controller after the condition is met. ### Claim 20 (depends on 19) An apparatus as recited in claim 19, wherein the at least one of the processors and memory are further adapted for: simulating operation of the hardware devices based on simulating execution of the program sequence while performing the one or more interlock check(s) for each set of translated instructions to determine whether an interlock check fails; and inhibiting execution of the process when an interlock check fails.