Secure keypad scanning
AssigneeMaxim Integrated Products, Inc.
InventorJeremy J. Miller
Life of this patent
Estimating the term…
Abstract
A secure key scanning functionality drives the row lines and column lines of a key switch array with randomized pulses of different polarities, and drives signals in one direction from a row line through a pressed key and to a column line as well as in an opposite direction from the column line through the pressed key and to the row line. To make unauthorized detecting of key presses more difficult, row lines and column lines are driven with pulses that appear as actual key press conditions when in fact the pulses are dummy pulses and no corresponding key has been pressed. In one novel aspect, dummy pulses are generated so that the line being driven with the dummy pulses has the same sustained and consistent waveform as the intersecting row and column lines that have identical waveforms due to the actual key press.
Claims24
A method comprising:
- (a) driving a first signal out onto a first row line, wherein the first row line is one of a plurality of row lines of a row line/column line matrix (RLCLM) of a key switch array;
- (b) detecting the first signal on a first of a plurality of column lines of the RLCLM;
- (c) driving a second signal out onto said first column line;
- and
- (d) detecting the second signal on first row line.
A method comprising:
- (a) performing a key scanning operation by driving pulse signals into a row line/column line matrix (RLCLM) of a key switch array and monitoring a plurality of lines of the RLCLM;
- (b) detecting a first pulse signal on one of the plurality of lines during the monitoring of (a);
- and
- (c) in response to the detecting in (b) changing the key scanning operation by driving a second pulse signal onto said one of the plurality of lines.
An integrated circuit comprising:
- a plurality of input/output cells;
- a plurality of terminals, wherein each terminal is coupled to a corresponding respective one of the plurality of input/output cells;
- a memory that stores a set of processor-readable instructions, wherein the set of processor-readable instructions is a key scanning routine;
- and
- a processor that executes the set of processor-readable instructions such that:
- 1) a first pulse signal is driven out of a first of the input/output cells and a first of the terminals, and during the driving of the first pulse signal a second of the input/output cells is monitoring a second of the terminals to determine whether the first pulse signal is received on the second terminal, and 2) a second pulse signal is driven out of the second input/output cell and the second terminal, and during the driving of the second pulse signal the first input/output cell is monitoring the first terminal to determine whether the second pulse signal is received on the first terminal.
An integrated circuit comprising:
- a memory that stores a set of processor-readable instructions, wherein the set of processor-readable instructions is a key scanning routine;
- and
- a processor that executes the set of processor-readable instructions;
- a polarity bit;
- an input/output bit;
- an input read bit;
- a terminal;
- and
- an input/output cell that is coupled to the terminal and that includes a logic circuit, wherein if the input/output bit has a first value then the logic circuit supplies either the value of the polarity bit or the inverse of the value of the polarity bit to the input read bit, whereas if the input/output bit has a second value then the logic circuit is usable to supply a value on the terminal to the input read bit.
A method for Key Switch array detection comprising:
- providing a logic circuit within input/output cell of an integrated circuit, wherein if the input/output cell is configured as an input cell then the logic circuit supplies a value on a terminal to an input read bit, whereas if the input/output cell is configured as an output cell then the logic circuit is usable to supply a selectable one of either a value of a polarity bit or the inverse of the value of the polarity bit to the terminal.
A method for Key Switch array detection comprising:
- providing a logic circuit within an input/output cell of an integrated circuit, wherein if the input/output cell is configured as an input cell and a mask bit has a first value then the logic circuit supplies a value on a terminal to an input read bit, whereas if the input/output cell is configured as an input cell and the mask bit has a second value then the logic circuit supplies a mask value to the input read bit, whereas if the input/output cell is configured as an output cell then the logic circuit supplies either a value of a polarity bit or the inverse of the value of the polarity bit to the terminal.
An integrated circuit comprising:
- a plurality terminals;
- and
- means for using the plurality of terminals in a key scanning operation, wherein in response to a keypress condition the key scanning operation causes signal waveforms on at least three of the terminals to be substantially identical for a period of at least one quarter of a second.
Dependencies are inferred from the claim text.