Wiring information generating apparatus, method and program

A wiring information generating method that connects a plurality of logic element devices arranged on a substrate of a semiconductor logic circuit, the wiring information generation method comprising:

• inputting a wiring layer number indicating a wiring layer in which wiring is to be carried out, a via layer number indicating a next via layer to connect the wiring layer with other wiring layer, and spacing information based on wiring rules;
• storing a terminal figure table providing a terminal figure of a logic element device, a logic element device wire protected area table providing logic element device wire protected areas inside the logic element device, and a wire protected area table providing wire protected area information for the semiconductor logic circuit;
• searching the terminal figure table and the logic element device wire protected area table based on the input wiring layer number and/or via layer number;
• adding to the wire protected area table an area of a terminal figure and a logic element device wire protected area, obtained by searching of the terminal figure table and the logic element device wire protected area table;
• acquiring first wire layer-via layer spacing information representing spacing between one of a plurality of wiring layers and one of a plurality of via layers based on the wiring layer number and/or via layer number;
• adding the first wire layer-via layer spacing information to the wire protected area table;
• and
• generating wiring information in a wiring layer among the plurality of wiring layers based on connection information and arrangement information of the semiconductor logic circuit, and the wire protected area information.

A non-transitory computer readable recording medium that stores a wiring information generating program that causes a computer to execute:

• inputting a wiring layer number indicating a wiring layer in which wiring is to be carried out, a via layer number indicating a next via layer to connect the wiring layer with other wiring layer, and spacing information based on wiring rules;
• storing a terminal figure table providing a terminal figure of a logic element device, a logic element device wire protected area table providing logic element device wire protected areas inside the logic element device, and a wire protected area table providing wire protected area information for the semiconductor logic circuit;
• searching the terminal figure table and the logic element device wire protected area table based on the input wiring layer number and/or via layer number to the wire protected area table;
• adding to the wire protected area table an area of a terminal figure and a logic element device wire protected area, obtained by searching of the terminal figure table and the logic element device wire protected area table;
• acquiring first wire layer-via layer spacing information that is spacing between one of a plurality of wiring layers and one of a plurality of via layers based on the wiring layer number and/or via layer number;
• adding the first wire layer-via layer spacing information to the wire protected area table;
• and
• generating wiring information in a wiring layer based on connection information and arrangement information of the semiconductor logic circuit, and the wire protected area information.