High-speed low-leakage-power standard cell library

A resulting integrated circuit designed using an extended standard cell library, wherein the extended cell library has a predefined track height, comprising:

• a set of cells in the resulting integrated circuit that are associated with a logic function, wherein the set of cells includes:
• a first cell having a maximum drive strength for the logic function in the extended standard cell library,
• a second cell having a minimum leakage power, wherein the minimum leakage power is determined by a minimum device area required for the logic function, and
• a plurality of third cells having a drive strength between the maximum drive strength for the logic function and a drive strength of the second cell and a leakage power between the minimum leakage power and a leakage power of the first cell,
• wherein the second cell includes padding between a voltage rail of the second cell and a cell device.

A method for forming a resulting integrated circuit using an extended standard cell library, wherein the extended standard cell library has a predefined track height, comprising:

• forming at least one cell in the resulting integrated circuit from a first plurality of cells associated with a first set of logic functions, wherein each cell in the first plurality of cells has a first device area based on a maximum device area for the predefined track height of the extended cell library;
• identifying a second set of logic functions;
• and
• forming at least one cell in the resulting integrated circuit from a second plurality of cells associated with a second set of logic functions, wherein, for each cell in the second plurality of cell, forming includes:
• placing padding in the cell between a device in the cell and a power rail of the cell to achieve a set of desired characteristics for the cell,
• wherein each cell in the second plurality of cells has different characteristics.