Loading patent…
AssigneeCadence Design Systems, Inc.
InventorsYa-Chieh Lai, Frank E. Gennari, Matthew W Moskewicz, Junjiang Lei, Weinong Lai
Estimating the term…
Disclosed is an approach for performing pattern classification for electronic designs. One advantage of this approach is that it can use fast pattern matching techniques to classify both patterns and markers based on geometric similarity. In this way, the large number of markers and hotspots that typically are identified within an electronic design can be subsumed and compressed into a much smaller set of pattern families. This significantly reduced the number of patterns that must be individually analyzed, which considerably reduces the quantity of system resources and time needed to analyze and verify a circuit design.
A method for performing pattern classification of patterns within an integrated circuit design, comprising:
A computer program product that includes a non-transitory computer readable medium, the non-transitory computer readable medium comprising a plurality of computer instructions which, when executed by a processor, cause the processor to execute performing a process for performing pattern classification of patterns within an integrated circuit design, the process comprising:
A system for performing pattern classification of patterns within an integrated circuit design, comprising:
Dependencies are inferred from the claim text.