US 8,079,002 B1Granted

Method and apparatus for evaluating paths in an integrated circuit design

AssigneeXilinx, Inc.

InventorsKuok-Khian Lo, Mark B. Roberts, Mohammed Fakhruddin, James Karp, Richard P. Burnley, Min-Hsing Chen

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Abstract

An embodiment of the invention involves: providing a database that includes layout information representing a layout within an integrated circuit of an electrical circuit; identifying from the information in the database each conductive path of a selected type in the electrical circuit; extracting layout information from the database for each conductive path of the selected type; and calculating an electrical parameter for each conductive path of the selected type, as a function of the layout information obtained for that conductive path during the extracting. In addition, in a different configuration of the embodiment, a report can be generated containing information based on the electrical parameter calculated during the calculating for at least one of the conductive paths of the selected type.

Claims13

Dependent claims

An apparatus comprising:

computer-readable storage containing:
a database that includes layout information representing a layout within an integrated circuit of an electrical circuit, the integrated circuit having external pads and electro-static discharge (ESD) elements;
wherein the database has a first section containing schematic information representing a circuit schematic for the electrical circuit and a second section containing the layout information for the electrical circuit;
and
computer-executable instructions that, when executed, cause:
identifying from the schematic information in the database, conductive paths from the external pads of the integrated circuit to the electro-static discharge (ESD) elements in the electrical circuit;
extracting layout information describing the electrical circuit from the layout information in the database;
for each conductive path identified from the schematic information, identifying a corresponding network and a corresponding portion of the network in the extracted layout information;
calculating an associated resistance for each conductive path as a function of the layout information of the identified corresponding portion of the network for that conductive path;
determining whether the associated resistance of each conductive path exceeds a threshold;
and
outputting data indicative of each conductive path having the associated resistance determined to exceed the threshold.

9 more elements

A method comprising:

providing a database that includes layout information representing a layout within an integrated circuit of an electrical circuit, the integrated circuit having external pads and electro-static discharge (ESD) elements;
wherein the database has a first section containing schematic information representing a circuit schematic for the electrical circuit and a second section containing the layout information for the electrical circuit;
and
carrying out a sequence that includes:
identifying from the schematic information in the database, conductive paths from the external pads of the integrated circuit to the electro-static discharge (ESD) elements in the electrical circuit;
extracting layout information describing the electrical circuit from the layout information in the database;
for each conductive path identified from the schematic information, identifying a corresponding network and a corresponding portion of the network in the extracted layout information;
calculating, using a computer system, an associated respective resistance for each conductive path as a function of the layout information of the identified corresponding portion of the network for that conductive path;
determining whether the respective resistance of each conductive path exceeds a maximum resistance value;
and
generating a report that includes information indicative of each conductive path having the respective resistance determined to exceed the maximum resistance value.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/344,030Filed 24 Dec 2008
Granted: 13 Dec 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…
G06F 30/34
Circuit design: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06F 30/343
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: logical level
G06F 30/39
Circuit design: circuit design at the physical level