Integrated circuits and methods of design and manufacture thereof
AssigneeInfineon Technologies AG
InventorsHenning Haffner, Manfred Eller, Richard Lindsay
Life of this patent
Estimating the term…
Abstract
Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
Claims29
A method of forming a mask set, the method comprising:
- generating a layout using a representation of a selective double patterning technique;
- extracting a functionality of the layout;
- comparing the extracted functionality to a predetermined functionality;
- repeating generating, extracting and comparing until a satisfactory layout is generated;
- and
- forming the mask set based upon the satisfactory layout.
A method of forming a mask set, the method comprising:
- generating a layout using a representation of a selective double patterning technique, wherein the representation comprises a generic description, a model, a rule, an electrical behavior and/or a yield behavior;
- extracting a functionality of the layout;
- comparing the extracted functionality to a predetermined functionality;
- repeating generating, extracting and comparing until a satisfactory layout is generated;
- and
- forming the mask set based upon the satisfactory layout.
A method manufacturing an integrated circuit, the method comprising:
- generating a layout using a representation of a selective double patterning technique;
- extracting a functionality of the layout;
- comparing the extracted functionality to a predetermined functionality;
- repeating generating, extracting and comparing until a satisfactory layout is generated;
- forming the mask set based upon the satisfactory layout;
- and
- manufacturing an integrated circuit using the mask set.
A method of forming a mask set, the method comprising:
- generating a layout using a representation of a selective double patterning technique, wherein the selective double patterning technique comprises a rule-based description, and wherein the rule-based description includes dimensioning based on neighbors within a same design layer;
- extracting a functionality of the layout;
- comparing the extracted functionality to a predetermined functionality;
- repeating generating, extracting and comparing until a satisfactory layout is generated;
- forming the mask set based upon the satisfactory layout.
A method of forming a mask set, the method comprising:
- generating a layout using a representation of a selective double patterning technique, wherein the selective double patterning technique comprises a rule-based description, and wherein the rule-based description includes dimensioning or interaction with an other design layer;
- extracting a functionality of the layout;
- comparing the extracted functionality to a predetermined functionality;
- repeating generating, extracting and comparing until a satisfactory layout is generated;
- and
- forming the mask set based upon the satisfactory layout.
Dependencies are inferred from the claim text.