Memory system, memory system controller, and a data processing method in a host apparatus
AssigneeKabushiki Kaisha Toshiba
InventorHideo Aizawa
Life of this patent
Estimating the term…
Abstract
A memory system includes code data generating section which generates code data based on write data. A nonvolatile semiconductor memory stores the write data and the code data for the write data and outputs read data and the code data for the read data. An error correcting section is configured to correct an error bit included in the read data using the read data and the code data for the read data, and outputs the read data which includes the error bit in accordance with a setting. An interface section receives the write data from outside of the memory system, and outputs the read data to outside of the memory system.
Claims14
A memory system comprising:
- a code data generating section which generates code data based on write data;
- a nonvolatile semiconductor memory which stores the write data and the code data for the write data and outputs read data and the code data for the read data;
- an error correcting section which is configured to correct an error bit included in the read data using the read data and the code data for the read data;
- an interface section which receives the write data from outside of the memory system, and outputs the read data to outside of the memory system;
- and
- a mode control section which sets the memory system in one of a first operation mode and a second operation mode based on an instruction received from outside of the memory system, wherein,
- the interface section outputs the read data which is read from the nonvolatile semiconductor memory and includes an error bit to outside of the memory system in response to a read request received from outside of the memory system in the first operation mode,
- the error correcting section corrects an error bit included in the read data read from the nonvolatile semiconductor memory and the interface section outputs the read data including the error bit corrected to outside of the memory system in response to the read request in the second operation mode, and
- the instruction and the read request are included in the same command.
A memory system controller which controls a nonvolatile semiconductor memory mounted in a memory system, comprising:
- a code data generating section which generates code data based on write data;
- an error correcting section which is configured to correct an error bit included in read data using the read data and the code data for the read data which are read from the nonvolatile semiconductor memory;
- an interface section which receives the write data from outside of the memory system, and outputs the read data to outside of the memory system;
- and
- a mode control section which sets the memory system in one of a first operation mode and a second operation mode based on an instruction received from outside of the memory system, wherein,
- the interface section outputs the read data which is read from the nonvolatile semiconductor memory and includes an error bit to outside of the memory system in response to a read request in the first operation mode,
- the error correcting section corrects an error bit included in the read data read from the nonvolatile semiconductor memory and the interface section outputs the read data including the error bit corrected to outside of the memory system in response to the read request in the second operation mode, and
- the instruction and the read request are included in the same command.
A data processing method in a host apparatus into which a memory system is inserted, the memory system comprising a nonvolatile semiconductor memory and a memory system controller controlling the nonvolatile semiconductor memory, the method comprising:
- providing the memory system with a mode control command which sets the memory system in one of a first operation mode and a second operation mode;
- generating code data based on write data;
- instructing the memory system to write the write data and the code data for the write data into the nonvolatile semiconductor memory;
- instructing the memory system to read read data and the code data for the read data from the nonvolatile semiconductor memory;
- judging an operation mode of the memory system;
- and
- correcting an error bit included in the read data using the read data and the code data for the read data when the operation mode is the first operation mode, wherein,
- the read data which is read from the nonvolatile semiconductor memory and includes an error bit is output from the memory system in response to a read request received from the host apparatus to the memory system in the first operation mode,
- an error bit included in the read data read from the nonvolatile semiconductor memory is corrected and the read data including the error bit corrected is output from the memory system in response to a read request received from the host apparatus to the memory system in the second operation mode, and
- setting the operation mode of the memory system and instructing the memory system to read read data and the code data for the read data from the nonvolatile semiconductor memory are carried out by one command.
Dependencies are inferred from the claim text.