Interleaving redundancy apparatus and method
AssigneeLantiq Deutschland GmbH
InventorBernd Heise
Life of this patent
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Abstract
One embodiment of the invention relates to a network communication device. The network communication device includes a network interface configured to receive an initial data stream. The network communication device also includes an interleaving redundancy encoder that comprises a memory unit arranged in N columns and D rows. The interleaving redundancy encoder is configured to calculate at least one redundancy byte based on a series of spaced, non-consecutive bytes in the initial data stream. Other systems and methods are also disclosed.
Claims20
A network device, comprising:
- a network interface configured to receive an initial data stream;
- an interleaving redundancy encoder comprising a memory unit that arranges data in N columns and D rows;
- the interleaving redundancy encoder configured to calculate at least one redundancy bit based on a series of spaced, non-consecutive bits in the initial data stream.
An interleaving redundancy encoder adapted to facilitate transmission of data over a transmission medium, comprising:
- a memory unit having a number of memory cells arranged in a number of rows and a number of columns;
- a write controller configured to write a group of payload bits to the memory unit according to a first pattern, and further configured to write a group of redundancy bits to the unit according to a second, different pattern.
An interleaving redundancy encoder adapted to facilitate transmission of data over a transmission medium, comprising:
- a memory unit having a number of memory cells arranged in a number of rows and a number of columns;
- a first redundancy encoder configured to calculate at least one redundancy bit based on data values in a row of the memory unit;
- a second redundancy encoder configured to calculate at least one redundancy bit based on data values in a column of the memory unit;
- and
- a write controller configured to write payload bit to the memory unit according to a first pattern, and further configured to write redundancy bits to the memory unit according to a second, different pattern.
Dependencies are inferred from the claim text.