Semiconductor memory, semiconductor memory system, and error correction method for semiconductor memory

An error correction method of a semiconductor memory comprising:

• selecting a word line common to a plurality of memory blocks, a first parity block, and a second parity block in response to a read request;
• reading a first parity code from a first parity memory cell coupled to the word line in the first parity block;
• reading a second parity code from a second parity memory cell coupled to the word line in the second parity block;
• correcting the first parity code using the second parity code;
• and
• correcting the data held by a regular memory cell in the memory block using the corrected first parity memory cell code.

A semiconductor memory system comprising;

• a semiconductor memory;
• and
• a controller that controls access to the semiconductor memory,
• wherein the semiconductor memory comprises:
• a plurality of memory blocks that include a plurality of regular memory cells;
• a plurality of first parity blocks that are disposed in correspondence with the plurality of memory blocks, wherein the plurality of first parity blocks include a first parity memory cell holding a first parity code;
• a second parity block that includes a second parity memory cell for holding a second parity code having a parity bit corresponding to the first parity code;
• a parity error correction unit that corrects an error of the first parity code using the second parity code;
• and
• a data error correction unit that corrects an error of the data stored in a regular memory cell using the first parity code corrected by the parity error correction unit.