Decoder for low-density parity-check convolutional codes

A decoder for information bits represented by arbitrary length blocks of low-density, parity-check codes, the decoder comprising a plurality of interconnected processors, at least one of the plurality of interconnected processors further comprising:

• a plurality of interconnected nodes;
• and
• a memory interconnected with the plurality of interconnected nodes, the memory adapted to store intermediate log likelihood ratio (LLR) values based on channel LLR values representing the low-density, parity-check codes to enable outputting LLR values having improved accuracy relative to the channel LLR values, wherein the memory is adapted to store the intermediate LLR values in a circular buffer where a pointer tracks a current position in the circular buffer;
• wherein final LLR values from one of the plurality of interconnected processors can be used to decision the information bits.

A method of processing information represented by arbitrary length blocks of low-density, parity-check codes, the method comprising:

• passing a plurality of channel log likelihood ratio (LLR) values representing the information through a decoder comprising a plurality of processors;
• alternately passing each of a plurality of intermediate LLR values through a variable node and a parity-check node, at least in part by storing the plurality of intermediate LLR values in and retrieving the plurality of intermediate LLR values from a memory device in each processor of the plurality of processors, wherein the memory device is adapted to store the plurality of intermediate LLR values in a circular buffer where a pointer tracks a current position in the circular buffer;
• and
• decisioning the information based on output LLR values from at least one of the plurality of processors.